1.RFIC thin film process development (2021.6-2022.4)• Fab new CVD oxide/SiN, PVD oxide/SiN, and stress measurement tools qualification, process tuning and sustaining.• NH3 free SiNx low temperature CVD process development for passivation layer, achieve 3.2Mb/20nm coefficient of frequency modulation, and good step coverage on IDT to protect from PI corrosion.• F doping CVD TEOS oxide process development for Brag reflection layers and PZ under-layer, with F contents adjusting, film characterization and WAT analysis, obtaining the optimum recipe and increasing TCF>70%.• TCF improvement based on PVD SiO2 process, through DOE of PVD DC/RF/Bias power, gas ratio, target working position, localized etching, combining surface roughness treatment to improve TCF 4～5ppm/C without causing downsides on Q or Keff.2.PZT film process development (2022.1-now)• Collaborate with Japan X university and experts for Inject head piezo film development.• Using high temperature e-beam technique to fabricate high quality ZrO2 seed layer.• PZT film process optimization based on CSD method on ZrO2 seed, focusing on Zr/Ti ratio, bake temperature/gas phrase/pressure, RTA conditions and single spin thickness, combining XRD and piezo characterizations and obtaining nearly single crystal PZT film with high d31(>XXX), breakdown voltage (>XXX v/um), and low dielectric constant (

2017.07-2020.07 Intel Dalian1. New tool qualification, process sustaining.2. Tool abnormal impact disposition• Analyze the abnormal and the impact on production, make decision on lot disposition• Develop rework flow and recipe to save the production based on flow/CD/defect/param/probe and reliability data, etc.• Handling urgent cross area contamination case and minimize the impact.• Reaction mechanism creation for ME technician and give training. 3. HT 24K N2 carbon film process development• Develop HT 24K carbon film recipe to act as hard mask, and using N2 to replace POR H2 to make the carbon film as the sidewall/bottom SiO2/Si protection and the barricade of insitu etch “F”.• Large improvement pin hole issue.• Increase Qtime from 5h to 24h and totally free of tungsten protrusion.• Using HT to releases stress for better etch temp and CD profile control, and eliminate post carbon RTP step for better film integrity and less cost.• Wafer center Bindu/dw/db yield improved ~15%.4. Pillar carbon dep recipe improvement• Based on DOE for pressure and gas flow to tune film profile for thicker edge.• Extend DE tool part life time by thicker carbon edge, saving $8/wafer.• Carbon clean recipe improvement to ensure enough clean efficiency.5. Module cost management• Trace module cost on parts replacement.• Find opportunity for parts replacement or 2nd source.2019.03-2019.10 Intel RTD (Albuquerque/Salt Lake City, US)1. Intel RTD 3D XPoint start up• Process/recipe/PRD/SPC/FD data collection from Micron IMFT (F2).• RTD MES system (SPC, FD, APC,etc) set up.• RTD tool automation system test and debug.2. Intel F68 3D XPoint start up• CMOS/MOL/BEOL LAM CVD carbon steps process qualification.• Implement and qualify LL GEN5 to reduce carbon defect from LL, 0.4dpw block etch improvement.• BEOL metal5 carbon film spiral shape center defect improvement by DOE skews of pressure/pumping speed/posa, etc. (based on LAM tool)