Dr. Chen-Yong Cher was a Research Staff Member in the Computer Architecture Department at the IBM Thomas J. Watson Research Center from 2004 to 2016. He received B.S., M.S. and Ph.D. degrees in Electrical and Computer Engineering from Purdue University, in 1998, 2000 and 2004, respectively. He subsequently joined IBM at the Thomas J. Watson Research Center, where he has worked on performance, thermal, process variation, power and soft error reliability for microprocessors. He has contributed to BlueGene/Q microarchitecture definition and is principal power and soft error reliability architect for Power Edge-of-Network (EN) and BlueGene/Q compute chips. He has completed IBM Micro-MBA I and II management and accounting courses. He has been an IEEE senior member since 2013. He is an author or coauthor of 25 patents and over 40 technical papers.Specialties: Computer Architecture.SMT, Multi-core Processor Design and Analysis.Accelerator Design and Programming, software/hardware co-designs.Chip Power Analysis, Clock-gating, power-gating design, multi-vt flow, power review and sign-offs.Chip Reliability Analysis and design, review and sign-offs.Chip Yield and Variation Analysis.System-level Power Modeling and Management.System-level Thermal Management.Memory Management and Java Garbage Collection (GCC)Operating System Task Scheduler (Linux)