Chen-Yu Liang Email & Phone Number

My name is Chen-Yu Liang. I received my M.S. degree from National Chiao Tung University (NCTU) in Hsinchu, Taiwan, in 2019, and I am currently pursuing a Ph.D. at the Institute of Electronics at the same institution. My research focuses on electrostatic discharge (ESD) protection designs for high-speed I/O and RFIC in CMOS technologies. I have extensive hands-on experience with multiple tape-out experiences, including TN28 Ultra Low-C ESD Protection Design, Dual Direction ESD Protection for 40Gbps Applications, and a Wide Band Matching Network for High ESD Robustness. From 2019 to 2022, I served as a senior engineer at Micron Technology in Taiwan, working in the Electrical Failure Analysis (EFA) section of the Yield Enhancement Department. My role involved identifying and analyzing product failure mechanisms, which honed my skills in process integration, failure diagnostics, and reliability assessments. My technical expertise spans TCAD device simulation, process integration, device characterization, analog/RF circuit design, EM simulation, and ESD protection circuit design. I have worked across various technology nodes, including T18, TN28, and TN16, giving me a broad perspective on semiconductor design and manufacturing knowledge.Education:Doctor of Philosophy (PhD) in Electronic Engineering [2022- Present]National Yang-Ming Chiao-Tung University (NYCU), Hsinchu, TaiwanMaster of Science (MSc) in Electronic Engineering [2017-2019]National Chiao Tung University (NCTU), Hsinchu, Taiwan- GPA: 4.07Bachelor of Science (BSc) in Physics [2011-2015]National Tsing Hua University (NTHU), Hsinchu, TaiwanProfessional Experience:OMT Sr. EFA Engineer [2019-2022]Micron Technology, Taoyuan, Taiwan- Conducted electrical and physical failure analysis (EFA&PFA) on semiconductor products, specializing in DRAM probe test flow- Performed device characterization, reliability analysis, and failure physics investigation- Expertise in silicon process integration and semiconductor product engineeringSkills:- RF integrated circuit (RFIC)/ High-speed IO ESD protection- Semiconductor Product Engineering- DRAM Probe Test Flow- Electrical and Physical Failure Analysis (EFA&PFA)- Device Characterization, Reliability, and Failure Physics- Silicon Process Integration- DRAM Architecture and Technology- ESD/ Latch-up Protection- TCAD Simulation- DRAM Test Bench, Probe Tester- Thermal, EMMI, OBIRCH, SEM, B1500, 4284A- Cadence Schematic and LayoutAchievements and Certifications:- Graduated with a GPA of 4.07- TOEFL Score: 94

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  Senior Dram Electrical Failure Analysis

  Micron Technology

  Oct 2019 - Sep 2022 - 台灣 桃園市 桃園區