Chen Zou Email & Phone Number

Mountain View, CA, US

Edge TPU Compiler

Chicago, IL, US

• Architecting VarSIMD to accelerate computing in computational storage (C++, SystemVerilog, LLVM, RISCV-V)
• Established a classification framework on offload functions to identify SIMD ISA customization opportunities.
• Systematically comparing SIMD acceleration approach handling variable-width data elements for offloaded functions: fully software using RISCV-V, Pack/Upack isolation + RISCV-V, direct compute on var width elements.
• Did LLVM extensions, Gem5 extensions and SystemVerilog implementation for evaluations.Architecture support of stream computing to accelerate computational storage (C++, Python3, Gem5, MQSim)
• Identified the memory wall issues in computational SSDs when matching computing to flash bandwidth.
• Detailed workload analysis leads to insights into the feasibility of stream computing in computational storage.

Suwon-Si, Gyeonggi-Do, KR

• Shuffle acceleration on computational storage (Scala, JAVA, C++, SystemVerilog, OpenCL)
• Developed a Spark SQL profiler that aggregates CPU time to different functions using stack graphs.
• Demonstrated the shuffle bottleneck in distributed analytics that takes up to 60% of the total execution time.
• Architected a shuffle accelerator on SmartSSD FPGA that exploits system benefits of near-data computing and microarchitectural benefits of parallelism exploitation and custom memory hierarchies.
• Achieved 5x shuffle kernel-level speedup and 23% end-to-end analytical query speedup on average.

Mountain View, CA, US

• Neural network workload analysis for EdgeTPU (C++, Python3, gRPC)
• Developed a neural network model info crawler on Google’s codebase, which collected 700+ neural network models that are actively used in Google.
• Characterized neural network models with parameters, input/output shapes, and computing intensity.
• Predicted resource demands (computing/memory intensity) of future models to guide EdgeTPU design.

San Jose, California, US

• Data-driven routing congestion prediction at placement stage
• Performed data collection and cleaning from the placed design in Cadence design database.
• Designed an CNN architecture to predict routability using the resource maps during placement
• Did Hype-Parameter turning on the designed CNN architecture.

Edmonton, Ab, CA

• Approximate Logic Synthesis for two-level circuits, published on ASICON 2015
• Designed a dynamic programming based heuristic algorithm to perform approximate logic synthesis
• Employed multithreading to accelerate the implementation.

Doctor Of Philosophy (Ph.D.), Computer Science

Bachelor’S Degree, Microelectronics