Chester Szczepucha Email & Phone Number

Oversaw design and redesign of micro-controller portions of various video processing equipment, including routers, switchers, master controls and control panels. Drove feature sets and scheduled agreements with marketing teams. Architected design and implemented embedded software for mentioned devices. Specified crucial hardware elements of new designs. Researched and introduced new microprocessor technologies.Selected ARM Cortex M7 family processor for family of small routers, guiding junior hardware engineer through schematic capture for CPU section.Re-architected and implemented software for platform, from single loop with IRQs in C to RTOS-based multi-threaded object-oriented solution in C++11, with built-in web page server. As a result $4 mil/year product line life has been extended for several years.Reused mentioned below ARM+Linux platform (APC) to develop software for three products: two IP Gateway router boards and enhanced 64x64 Compact router.Specified main processor and created SW platform for new advanced router processing card (APC) using ARM CortexA8.Configured and brought up Linux for APC, developed proprietary driver, resolved problems with distribution drivers, implemented general product infrastructure, ported integrated serial / Ethernet message handler, and created internal web page for configuration and updates. Developed embedded software for elements of master control panels, facilitating re-legendable LCD button control, Ethernet client communication and FPGA infrastructure. Developed Compact router embedded software, taking original proof of concept to current family of devices using common network infrastructure. That included network protocol implementation, FPGA configuration and communication, code updates. System based on micro-controller plus FPGA architecture.Managed controller software for large video router, porting router controller software to new generations of hardware (VxWorks, PowerPC).

Nevada City, Ca

Designed and wrote test code for development platform for verification of802.15.3 wireless MAC ASIC (Virtex 6000 FPGA, Atmel ARM7 CPU, peripherals, memory banks). Designed and implemented ThreadX RTOS BSP for development board. Converted example NDIS Ethernet driver for use with 802.15.3 MAC PCI board.Designed system-wide test to identify data throughput bottlenecks for system with maximum data rate of 480 Mbps. (PC app -> PC driver -> PCI bus -> MAC hw data path -> TDMA based scheduler-> PHY interface).

Grass Valley Ca

Responsible for: ASIC block design verification, HPNA driver software for a router. Tools used: gcc, Logic analyzer, Oscilloscope. 2+ million chips soldDesigned and wrote HPNA driver. Main Features: DMA based with cache oriented CPU, designed with QOS in mind using multiple priority channels both in hardware and softwareSupported HPNA slice debug: adding probe pins, writing test software, interpreting LA tracesConceived and implemented debugger tools for Packet Filter Processor, part of the IP router ASIC. Main Features: Single step, breakpoints, resource state display

Grass Valley Ca

Wrote PSOS board support package for VOIP device based on PowerPC. Tools used: DIAB C++ Compiler/PowerPC Assembler, Single Step Debugger. Main Features: Ethernet chip driver, serial port driver, FLASH memory management, boot code for TMS320-C54 DSP processorPorted QNX Neutrino to the board, wrote PSOS and QNX drivers for proprietary Ethernet controllerParticipated in architecting Soft modem for MS Windows NT environment. Wrote code interfacing between NT serial port driver and modem supervisor. Designed and implemented dynamic way of switching data handling tasks in modem supervisor. Tools used: Visual C++, MASM, Softice Debugger, IASPOX, Telegra Fax MonitorPorted Remote Boot code for two PowerPC based boards (850 and 855T) Brought up Linux on above-mentioned boards. Tool used gcc, gdb and Codetap