 Lead a 10 engineers team, and develop bumping, flipchip and HBM process Build up flipchip process and production line for graphic DRAM (volume >6k) Build up hybrid process (flipchip + wirebond) and production line for PC DRAM. Lead and develop new tech. of bumping and flipchip. Flipchip Substrates supplier management and design rule maintains. Build up 3DIC process HBM2e/3E (volume ~1M) Qualify HBM3E package successfully. Drive HBM3E package yield… Show more  Lead a 10 engineers team, and develop bumping, flipchip and HBM process Build up flipchip process and production line for graphic DRAM (volume >6k) Build up hybrid process (flipchip + wirebond) and production line for PC DRAM. Lead and develop new tech. of bumping and flipchip. Flipchip Substrates supplier management and design rule maintains. Build up 3DIC process HBM2e/3E (volume ~1M) Qualify HBM3E package successfully. Drive HBM3E package yield improvement from 30% to 85%. Create business flow of new product introduction Show less

 Thin down project design by SIP solution Molding underfill (MUF) process development  Develop dual side mold capability for SIP solution Develop SIP solution for EMI shielding  Advanced Package structure development for SIP Build up design rule of Package on Package process  Substrates supplier management and design rule maintains. Implement sputter process for production. Implement A customer project form developing to mass production. Responsible… Show more  Thin down project design by SIP solution Molding underfill (MUF) process development  Develop dual side mold capability for SIP solution Develop SIP solution for EMI shielding  Advanced Package structure development for SIP Build up design rule of Package on Package process  Substrates supplier management and design rule maintains. Implement sputter process for production. Implement A customer project form developing to mass production. Responsible for customer owner of Apple and Google Product manger for WIFI SIP Show less

 Lead a 10 engineers team, and handle over 6K production line and new process development. Create WLCSP and Fan-out SIP process mass production line (6000pcs/ month) Fan out (SIP) front-end and backend process build up and management Yield Improvement WLCSP yield improvement from 98% to 99.7% Fan-out (SIP) yield improvement from 80% to 96% Advanced Package development Thin substrate process capability build up  Evaluate 12” wafer level backend… Show more  Lead a 10 engineers team, and handle over 6K production line and new process development. Create WLCSP and Fan-out SIP process mass production line (6000pcs/ month) Fan out (SIP) front-end and backend process build up and management Yield Improvement WLCSP yield improvement from 98% to 99.7% Fan-out (SIP) yield improvement from 80% to 96% Advanced Package development Thin substrate process capability build up  Evaluate 12” wafer level backend process Grind tape for high bump wafer  New fan-out filling material survey Substrate material supplier management Show less

 New project development Thin wafer (Si thickness <250um) 及u-trench (scribe line width=20um, can increase die count per wafer) process build up and qualification Implement Mems G-sensor backend process and pass qualification Implement and qualify backside protect layer for WLCSP  Reliability Validation Wafer Level CSP implement and qualification (Improve die size 4mmx4mm from Board level TC100 to TC500, drop test >30times) Wafer Level CSP frontend… Show more  New project development Thin wafer (Si thickness <250um) 及u-trench (scribe line width=20um, can increase die count per wafer) process build up and qualification Implement Mems G-sensor backend process and pass qualification Implement and qualify backside protect layer for WLCSP  Reliability Validation Wafer Level CSP implement and qualification (Improve die size 4mmx4mm from Board level TC100 to TC500, drop test >30times) Wafer Level CSP frontend (Passivation layer +RDL +UBM) build up and yield improvement (Product yield>99%, Pass level2 reliability) Responsible for customer owner of MARVELL、PAM、PXI、Invensense Show less

 New project development New Pb free material implement and verification to meet lead free process Process verification for New Teflon material. Rigid Flex process development (Thickness decrease 50%)  Implement any layer substrate process, to reduce substrate’s thickness to 30%. Advanced Package development Develop embedded substrate process, make layout area smaller to 50%.  System set up  Build up substrate dimension control system to increase… Show more  New project development New Pb free material implement and verification to meet lead free process Process verification for New Teflon material. Rigid Flex process development (Thickness decrease 50%)  Implement any layer substrate process, to reduce substrate’s thickness to 30%. Advanced Package development Develop embedded substrate process, make layout area smaller to 50%.  System set up  Build up substrate dimension control system to increase accuracy from 80% to 97%. Build up substrate thickness predict system to make accuracy from 70% to 90%. Build up substrate impedance predict system to reduce failure rate from 11% to 4%. Build up X-ray monitor control system to reduce leak rate from 10% to 2%. Responsible for customer owner of MOTOROLA、KYOCERA、HTC、SONY Show less