Chirag Patil

Chirag Patil Email and Phone Number

CPU Verification Engineer @ Andes Technology Corporation
Beaverton, Oregon, United States
Chirag Patil's Location
Beaverton, Oregon, United States, United States
Chirag Patil's Contact Details

Chirag Patil personal email

n/a
About Chirag Patil

Chirag Patil is a CPU Verification Engineer at Andes Technology Corporation. He possess expertise in logic synthesis, physical design, rtl design, placement and routing, systemverilog and 5 more skills.

Chirag Patil's Current Company Details
Andes Technology Corporation

Andes Technology Corporation

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CPU Verification Engineer
Beaverton, Oregon, United States
Website:
andestech.com
Employees:
287
Chirag Patil Work Experience Details
  • Andes Technology Corporation
    Andes Technology Corporation
    Beaverton, Oregon, United States
  • Andes Technology Corporation
    Cpu Verification Engineer
    Andes Technology Corporation Jun 2023 - Present
    Hsinchu, Hsinchu, Tw
    Validating internal subsystems of a RISC-V core IP.
  • Intel Corporation
    Cpu Verification Engineer
    Intel Corporation Dec 2018 - Mar 2023
    Santa Clara, California, Us
    Helped maintain C++ reference models and SystemVerilog testbenches for microarchitecture features.Setup and managed coverage scripting and automation for the Atom IP org.Wrote 50+ custom x86 sequences consumed by architecture validation tools.Performed other typical verification activities such as testplanning, feature specification, and post-silicon debug.
  • Intel Corporation
    Soc Ip Validation Engineer
    Intel Corporation Aug 2016 - Dec 2018
    Santa Clara, California, Us
    Developed and maintained UVM SystemVerilog testbench collateral for memory IPs.Performed testplanning and content development for IP-owned features implemented at the SOC level.Helped design a new testbench methodology for APIC validation saving 2 months of project time.Assisted in developing coverage automation and feedback tools.
  • Intel Corporation
    Soc Logic Design And Verification Intern
    Intel Corporation Jun 2015 - Aug 2015
    Santa Clara, California, Us
    Wrote basic UVM sequence overrides to verify assertion control of a PCIe subsystem model using SystemCRefactored outdated SystemRDL register models for future microarchitecture development. Set up an integrated Makefile environment with Synopsys DVE for netlist linting and ECO validation.
  • Atmel Corporation
    Associate Engineering Intern
    Atmel Corporation Jun 2014 - Aug 2014
    San Jose, Ca, Us
    Used Cadence Virtuoso and Layout to modify existing bitline conditioning circuits and sense amplifiers in an SDRAM to pass JEDEC latchup requirements, also simulated their functionality in HSPICE.Used HSPICE to verify functionality of I/O padframe circuitry during critical latchup conditions.Worked on layout design techniques for meeting frequency, chip area, power, timing, signal integrity, voltage integrity, and functionality requirements.Wrote an automated test program for latchup wafer testing in NI Labview to interface with probe test hardware.
  • University Of Colorado Colorado Springs
    Physics Researcher
    University Of Colorado Colorado Springs Jun 2011 - Aug 2011
    Colorado Springs, Co, Us
    Fabricated copper-on-glass RF circuits and nickel nanowires on glass substrates.Helped design a test apparatus for liquid crystals involving liquid crystal thin-films in glass cells.Created piezoelectric crystals and quantum dots.

Chirag Patil Skills

Logic Synthesis Physical Design Rtl Design Placement And Routing Systemverilog Power Planning Algorithms Powerpoint Ovm/uvm Testbench Design

Chirag Patil Education Details

  • Portland State University
    Portland State University
    Electrical And Electronics Engineering
  • University Of Illinois Urbana-Champaign
    University Of Illinois Urbana-Champaign
    Electrical Engineering

Frequently Asked Questions about Chirag Patil

What company does Chirag Patil work for?

Chirag Patil works for Andes Technology Corporation

What is Chirag Patil's role at the current company?

Chirag Patil's current role is CPU Verification Engineer.

What is Chirag Patil's email address?

Chirag Patil's email address is ch****@****ntel.ca

What schools did Chirag Patil attend?

Chirag Patil attended Portland State University, University Of Illinois Urbana-Champaign.

What are some of Chirag Patil's interests?

Chirag Patil has interest in Place And Route Algorithms, Analog Design, Embedded Device Validation, Vlsi Digital Design And Verification.

What skills is Chirag Patil known for?

Chirag Patil has skills like Logic Synthesis, Physical Design, Rtl Design, Placement And Routing, Systemverilog, Power Planning, Algorithms, Powerpoint, Ovm/uvm, Testbench Design.

Who are Chirag Patil's colleagues?

Chirag Patil's colleagues are Tzu Yu Yang, Che-Chia Chang, 黃宇澤, Heng-Kuan Lee, Wei-Hao Chiao, 曾絲敏, Shang Wei Lin.

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