Chi Wei Weng
AeroLeads people directory · profile

Chi Wei Weng Email & Phone Number

Ex-Silicon Engineering Intern @ Google | MS ECE @ UCLA | VLSI, ASIC, FPGA, Computer Architecture
Location: Los Angeles, California, United States 4 work roles 2 schools
LinkedIn matched
✓ Verified July 2026 3 data sources Profile completeness 71%

Contact Signals

LinkedIn Profile matched
3 free lookups remaining · No credit card
Role
Ex-Silicon Engineering Intern @ Google | MS ECE @ UCLA | VLSI, ASIC, FPGA, Computer Architecture
Location
Los Angeles, California, United States

Who is Chi Wei Weng? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Chi Wei Weng is listed as Ex-Silicon Engineering Intern @ Google | MS ECE @ UCLA | VLSI, ASIC, FPGA, Computer Architecture based in Los Angeles, California, United States. AeroLeads shows a matched LinkedIn profile for Chi Wei Weng.

Chi Wei Weng previously worked as Silicon Engineering Intern at Google and Undergraduate Research Assistant at National Taiwan University. Chi Wei Weng holds Master Of Science - Ms, Electrical And Computer Engineering from Ucla.

Profile bio

About Chi Wei Weng

I am Chi Wei (Wesley) Weng, a dual citizen of the USA and Taiwan, currently pursuing my Master’s degree in Electrical and Computer Engineering at UCLA with a focus on Circuits and Embedded Systems. My expertise spans VLSI circuits, hardware emulation, and FPGA, with strong proficiency in hardware description languages like SystemVerilog and Verilog.During my Silicon Engineering internship at Google, I developed a SystemVerilog wrapper for PCIe Gen5 emulation. This involved integrating both physical and virtual bridge methods, setting up the environment for synthesis, and validating connectivity between the DUT and a virtual host via socket, improving system reliability and enabling faster debugging.Throughout my academic career at UCLA and National Taiwan University (NTU), I have worked on projects involving CNN accelerator, chip partitioning algorithm, and Gauss-Seidel iteration machine, continuously optimizing hardware efficiency and performance. I also earned the Iron Award at the 2022 InnovateFPGA Design Contest for developing a self-driving floating waste collector using FPGA, competing against 256 teams in Greater China.

4 roles

Chi Wei Weng work experience

A career timeline built from the work history available for this profile.

Silicon Engineering Intern

Google

Sunnyvale, California, United States

➣ Developed and integrated a SystemVerilog wrapper for the PCIe Gen5 emulation platform, enhancing flexibility by incorporating both physical speed bridge (SB) and newly designed virtual bridge (VB) methods, allowing seamless selection of the most suitable approach.➣ Designed the virtual bridge PCIe method, significantly improving system reliability by reducing hardware instability and enabling faster, more precise debugging, while supporting efficient multi-host connectivity.➣ Set up and validated the environment for compilation, synthesis, and elaboration, ensuring SB functionality remained intact and enabling the device under test (DUT) to connect with the virtual host QEMU via socket, achieving Gen5 data rates.

Jun 2024 - Sep 2024

Undergraduate Research Assistant

National Taiwan University

Taipei, Taipei City, Taiwan

Advisor: Prof. Chao-Lung Ting➣ Participated in NTU Intelligent Processing Laboratory within the Department of Engineering Science and Ocean Engineering, researching on machine learning.➣ Built a Yolov4-based car flow calculator; trained, labeled and traced targets on the COCO dataset using the Euclidean distance.

Jul 2022 - Oct 2022

Undergraduate Research Assistant

National Taiwan University

Taipei, Taipei City, Taiwan

Advisor: Prof. Jau-Horng Chen➣ Participated in NTU High-Efficiency Circuits and Systems Laboratory within the Department of Engineering Science and Ocean Engineering, researching on digital integrated circuit and FPGA design.➣ Designed a 3D-printed “Self-driving Floating Waste Collector” with an FPGA DE10-Nano board and in-house motor control, with an Ethernet cable connecting the two, receiving the Iron Award out of 256 competing teams in the 2022 InnovateFPGA Design Contest (Greater China).

Jul 2020 - Aug 2022

Summer Intern Engineer

Suruga Seiki., Https://Www.Linkedin.Com/Redir/General-Malware-Page?Url=Co%2Eltd

Taipei, Taipei City, Taiwan

➣ Built and adopted an automated planar calibration system for the company’s precision positioning products to replace previous manual operations, considerably increasing the precision.➣ Designed a stage control alignment system with an intuitive, friendly C-based interface, and added useful functions like real-time position tracking, position movement and alignment.

Jul 2021 - Aug 2021
2 education records

Chi Wei Weng education

Master Of Science - Ms, Electrical And Computer Engineering

Ucla
FAQ

Frequently asked questions about Chi Wei Weng

Quick answers generated from the profile data available on this page.

What is Chi Wei Weng's role at their current company?

Chi Wei Weng is listed as Ex-Silicon Engineering Intern @ Google | MS ECE @ UCLA | VLSI, ASIC, FPGA, Computer Architecture.

Where is Chi Wei Weng based?

Chi Wei Weng is based in Los Angeles, California, United States.

What companies has Chi Wei Weng worked for?

Chi Wei Weng has worked for Google, National Taiwan University, and Suruga Seiki., Https://Www.Linkedin.Com/Redir/General-Malware-Page?Url=Co%2Eltd.

How can I contact Chi Wei Weng?

You can use AeroLeads to view verified contact signals for Chi Wei Weng, including work email, phone, and LinkedIn data when available.

What schools did Chi Wei Weng attend?

Chi Wei Weng holds Master Of Science - Ms, Electrical And Computer Engineering from Ucla.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.

People with similar names

Check these profiles if this is not the Chi Wei Weng you were looking for.

View similar profiles