Chong W. Lim Email and Phone Number
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Experienced R&D & HVM professional with ~20 years of silicon and compound semiconductor industry technology development experiences in logic, non-volatile memory as well as photovoltaic devices. Recognized for expertise in thin-film technology development, process integration and device characterization with more than 30 patents, journal publications and conference presentations. Demonstrated strengths in developing cutting-edge technologies and managing new process implementation including planning, developing, tool installation & qualification to enable production ramp-up at global HVM sites.Proven track record and expertise in:• Explored and screened novel thin-film materials to determine the roadmap for future materials development by establishing fundamental structure-process-property relationships.• Developed new thin-film deposition techniques - including DC, pulsed-DC, RF, co-sputtering PVD and closed-space sublimation - to improve properties of metallic and semiconducting materials, including metal-silicides, CdTe/CdS and complex ternary/quaternary alloy thin-films.• Led cross-functional teams to investigate and rectify integrated process issues related to materials stability, film-electrode interface quality, as well as defectivity modes.• Facilitated technology-transfer from development to ISO9001 certified high-volume production by establishing SPC methodology and introducing new metrology capability to assess materials/process performance.• Leading and driving collaborative projects involving external suppliers to enhance existing process capability, hardware functionality and raw material quality.
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Director, Manufacturing EngineeringFirst Solar Aug 2012 - PresentTempe, Arizona, Us
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Manager, Process DevelopmentFirst Solar May 2009 - Aug 2012Tempe, Arizona, Us• Managing a development team of ~20 members. Responsibilities include hiring, developing and mentoring the team. Planning and providing technical guidance to multiple development projects, including both near-term and path-finding phase developments, cycle time and throughput enhancement, as well as line-yield improvement.• Developed novel in-situ doping technique during CdTe deposition to enhance device short-circuit current and improved module efficiency by up to 0.5%. Led HVM engineering teams over 10 months stay at Germany and Malaysia to resolve multiple process and tool incompatibility issues and successfully delivered the first 80W photovoltaic module and set best-in-fleet record performance of >12% module efficiency.• Led thin films activation group to develop next-generation annealing chamber to provide a more consistent and uniform doping ambient which, in turn, improved device long-term stability by up to ~5% - equivalent to ~$300M NPV increment via derate-improvement - without draw-back in module efficiency performance.• Implemented in-line band-gap and PL intensity measurement metrologies to enable tool-matching, process alignment and yield improvement across global fleet. Rolled-out new temperature profiling method and zone-by-zone SPC methodology to achieve >2x reduction in process variability at both front-end and back-end thin-film activation processing steps.
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Sr. Research EngineerNumonyx (An Intel Spinoff Company) 2008 - May 2009Rolle, Ch• Delivered industry-first phase-change memory cross-point array device functionality through enabling the deposition and integration of proprietary memory-switch-electrode materials system. • Obtained 40% improvement in deposited film thickness and electrical resistance uniformity through process and equipment development. Managed and led consortial hardware development projects, including sputter-magnet field-strength optimization and dual-zone biasable high-temperature e-chuck integration. • Addressed a 45% critical line-yield limiter due to arcing defects and film voids. Resolved root cause via extensive film/defect characterization and hands-on tool-level analysis to improve hardware design and plasma/film stability. -
Sr. Process EngineerIntel Corporation 2004 - Apr 2008Santa Clara, California, Us• Developed, an Intel-first, in-house low-pressure pulsed-DC sputtering system to fulfill the stringent gap-fill, thickness uniformity, and compositional requirements for ternary/quaternary chalcogenide thin-films deposition.• Enabled high-volume production of sub-90nm floating-gate memory devices by optimizing and improving mid-section Ni, Ti and Co salicide contact metallization schemes. • Attained Intel best-in-class performance across multiple HVM factories with record 94% availability. Executed installation/qualification of new PVD systems and managed module daily operations involving up to 15 technicians.• Delivered >$500k/yr of cost reduction via implementation of multiple cost-saving projects, including streamlined manufacturing operations and established statistical process control methodology to minimize product scrap. -
Integration EngineerChartered Semiconductor 1996 - 1999Us• Engineered Chartered's first generation borderless-contact technology for 0.22µm CMOS logic devices to achieve 15% reduction in die size and 30% improvement in device performance. • Delivered 20% sort-yield enhancement for 0.25µm logic devices by leading cross-disciplinary team to diagnose and resolve integrated process issues related to silicide-induced gate-to-source/drain current leakage.• Designed 0.25 & 0.22µm Ti silicide contact and backend Al metalization architectures and managed technology-transfer to enable new factory start-up. Led 0.18µm path-finding effort that resulted in the implementation of new salicide and inter-layer dielectric schemes with improved leakage and power performance.
Chong W. Lim Skills
Chong W. Lim Education Details
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University Of Illinois Urbana-ChampaignMaterials Science & Engineering -
National University Of SingaporeMaterials Science
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Nanyang Technological University SingaporeMaterials Science & Engineering
Frequently Asked Questions about Chong W. Lim
What company does Chong W. Lim work for?
Chong W. Lim works for First Solar
What is Chong W. Lim's role at the current company?
Chong W. Lim's current role is Director, Manufacturing Engineering at First Solar.
What is Chong W. Lim's email address?
Chong W. Lim's email address is ch****@****ail.com
What is Chong W. Lim's direct phone number?
Chong W. Lim's direct phone number is (877) 850*****
What schools did Chong W. Lim attend?
Chong W. Lim attended University Of Illinois Urbana-Champaign, National University Of Singapore, Nanyang Technological University Singapore.
What skills is Chong W. Lim known for?
Chong W. Lim has skills like Technology Management, Process Optimization, Semiconductor Fabrication, Semiconductor Device, Process Improvement, Device Characterization, Cvd, Rf, Semiconductors, Thin Films, Spc, Manufacturing.
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