Chris Baldwin Email & Phone Number

Chandler, Az, Us

Santa Clara, California, Us

Managed a staff of assembly engineers, design project managers, and technicians driving development and certification of advanced electronic-packaging solutions in support of Intel’s server, networking, FPGA, and AI roadmap• Completed certification and high-volume deployment of Intel’s Broadwell, Skylake, and Knights Landing server families. This included package-on-interposer technology, which has resulted >$200M in cost savings vs. traditional packaging.• Completed certification and high-volume deployment of Intel’s first three generations of Embedded Multi-die Interconnect Bridge (EMIB) technology in support of Altera FPGAs, Kaby Lake G mobile CPU, Sequoia Acres 5G ASIC, and the Sapphire Rapids and Emerald Rapids Xeon server families.• Managed development of Intel’s next-generation EMIB-scaling envelope on Intel and TSMC silicon nodes: a key technology for enabling compute and memory scale-out for next-gen AI processors.• Enabled robust internal supply chains and managed budgets exceeding $5M annually.

Santa Clara, California, Us

Managed a staff of twenty design engineers responsible for research and development of Intel’s electronic packaging solutions for all microprocessors and chipsets.• Team focus was optimization of product cost, performance, and form factor, as well as defining the test packages and boards used for certification of the substrate manufacturing and assembly/test processes.• This team was critical to developing and certifying all of Intel’s client and server microprocessors.

Santa Clara, California, Us

Defined and developed advanced packaging and socketing technology in support of Intel’s CPU roadmap• Managed the design of electronic packages for the 90nm desktop and server Pentium® 4 microprocessors. Tasks included design/manufacturing schedule management, cost/performance optimization, and resolution of silicon and system platform integration issues.• Led the early packaging pathfinding and development activities for the next generation of 65nm Itanium® microprocessors, including a novel top-side power-delivery connector.• Led the pathfinding efforts on the industry’s first high-volume land-grid-array (LGA) socket. Responsibilities included driving the design and reliability testing activities to prove feasibility.

Santa Clara, California, Us

Junior engineer responsible for design rule and test vehicle ownership for desktop client packaging technology• Oversaw design rule and test vehicle development for the Pentium® II, Pentium® III, and Pentium® 4 processor packaging technologies. Tasks included test vehicle definition and documentation, design rule definition and documentation, and supplier interaction on design issues.• Led package design attributes definition for the development of FCPGA technology, the industry’s first organic flip-chip pin-grid-array (PGA) package.

Master'S Degree, Mechanical Engineering

Bachelor'S Degree, Mechanical Engineering