I've spent my entire career focusing on advanced packaging development, certification, and ramp. Over that time, I worked hands-on with substrate/assembly design rules, definition and design of test vehicles for process development and certification, and product-technology optimization for cost, manufacturability, high-speed signaling, power delivery, reliability, and yield. As a program manager, I led major assembly/test development programs for server, mobile, desktop, AI, FPGA, networking, and ASIC programs, starting from definition all the way through full certification and transfer into high-volume manufacturing. The last ten years were spent taking EMIB (Embedding Multi-die Interconnect Bridge) technology from a pathfinding concept to an established volume runner.Along the way, I also developed a real appreciation for managing teams, both directly and within a matrixed environment. I've truly enjoyed teaching and coaching my team members, watching them grow into strong contributors both at Intel as well as across the industry. I strongly believe that you need to be invested in people's personal goals and ambitions to help position and motivate them to do their best work.While I'm currently enjoying retirement, I'm not sure I'm quite ready to disengage from the workforce for good. I'm open to interesting opportunities in program/people management, whether that be full-time, parti-time, or consulting. My background is clearly in advanced electronic packaging, but I'm very open to new industries where my skills would translate.
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Vice President, ProductBoston MaterialsChandler, Az, Us
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RetirementCareer Break Oct 2024 - Present
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Senior Director, Electronic Packaging Assembly And Test Program ManagerIntel Corporation Jan 2012 - Oct 2024Santa Clara, California, UsManaged a staff of assembly engineers, design project managers, and technicians driving development and certification of advanced electronic-packaging solutions in support of Intel’s server, networking, FPGA, and AI roadmap• Completed certification and high-volume deployment of Intel’s Broadwell, Skylake, and Knights Landing server families. This included package-on-interposer technology, which has resulted >$200M in cost savings vs. traditional packaging.• Completed certification and high-volume deployment of Intel’s first three generations of Embedded Multi-die Interconnect Bridge (EMIB) technology in support of Altera FPGAs, Kaby Lake G mobile CPU, Sequoia Acres 5G ASIC, and the Sapphire Rapids and Emerald Rapids Xeon server families.• Managed development of Intel’s next-generation EMIB-scaling envelope on Intel and TSMC silicon nodes: a key technology for enabling compute and memory scale-out for next-gen AI processors.• Enabled robust internal supply chains and managed budgets exceeding $5M annually. -
Director, Design Engineering Manager For Electronic PackagingIntel Corporation Sep 2004 - Dec 2011Santa Clara, California, UsManaged a staff of twenty design engineers responsible for research and development of Intel’s electronic packaging solutions for all microprocessors and chipsets.• Team focus was optimization of product cost, performance, and form factor, as well as defining the test packages and boards used for certification of the substrate manufacturing and assembly/test processes.• This team was critical to developing and certifying all of Intel’s client and server microprocessors.
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Electronic Packaging Design IntegratorIntel Corporation May 2001 - Aug 2004Santa Clara, California, UsDefined and developed advanced packaging and socketing technology in support of Intel’s CPU roadmap• Managed the design of electronic packages for the 90nm desktop and server Pentium® 4 microprocessors. Tasks included design/manufacturing schedule management, cost/performance optimization, and resolution of silicon and system platform integration issues.• Led the early packaging pathfinding and development activities for the next generation of 65nm Itanium® microprocessors, including a novel top-side power-delivery connector.• Led the pathfinding efforts on the industry’s first high-volume land-grid-array (LGA) socket. Responsibilities included driving the design and reliability testing activities to prove feasibility.
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Electronic Packaging Design EngineerIntel Corporation Jun 1997 - May 2001Santa Clara, California, UsJunior engineer responsible for design rule and test vehicle ownership for desktop client packaging technology• Oversaw design rule and test vehicle development for the Pentium® II, Pentium® III, and Pentium® 4 processor packaging technologies. Tasks included test vehicle definition and documentation, design rule definition and documentation, and supplier interaction on design issues.• Led package design attributes definition for the development of FCPGA technology, the industry’s first organic flip-chip pin-grid-array (PGA) package.
Chris Baldwin Education Details
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Auburn UniversityMechanical Engineering -
Auburn UniversityMechanical Engineering
Frequently Asked Questions about Chris Baldwin
What company does Chris Baldwin work for?
Chris Baldwin works for Boston Materials
What is Chris Baldwin's role at the current company?
Chris Baldwin's current role is Vice President, Product.
What schools did Chris Baldwin attend?
Chris Baldwin attended Auburn University, Auburn University.
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