As the Microarchitecture/RTL lead for a new OOO Arch unit I explored, evaluated, selected, documented, implemented, and refined the microarchitecture and RTL to deliver a performant and power/area/timing converged design. As the Microarchitecture/RTL lead for ISA instruction to micro-op cracking hardware design I worked and influenced across ISA, Arch, RTL design, uCode, and validation to spearhead development of this foundation hardware/software co-design logic used in both design and validation.

In my role as a SoC Design Engineer at Intel Corporation I lead project layout integration, convergence, and execution on 4 CPU SOC projects. I developed and championed first process node layout integration spec used across multiple SOC’s and IP’s. Additionally, I consistently reduced final physical hardening time of high complexity layout partition designs from weeks to days.

In my role as a Silicon Architecture Design Engineer at Intel Corporation, I owned and delivered large highly ported hybrid RF/SDP designs in the OOO RAT on 4 P-Core projects. I pioneered advancements in auto routing, metal fill, and Design Engineer layout ownership, resulting in a significant reduction of final physical hardening time from months to days.