I lead the Infrastructure Engineering team within the Telecom Systems Business (TSB) for Dell Technologies, responsible for the end-to-end architecture, performance, and security of the hardware platforms and systems for our telecom solutions offering. I lead a team of engineering architects focused on compute/storage/networking platforms, HW/SW performance, and product security that are optimized for the telecom RAN market. We partner with customers, solutions engineering and co-innovation teams, product management, and Dell's server, storage, and networking engineering development teams to ensure the end-to-end performance and security of our total solution.

Leader of the global software research team within the CTO Office, focused on advanced technology explorations in the areas of cloud native architectures, machine learning, and open source software. With team members in the US, China, Israel, and Brazil, we work closely and collaboratively with technology leaders across Dell EMC to identify and explore nascent technologies, and demonstrate through exemplary proof-of-concepts the viability and applicability of these technologies to company, customer, and industry use cases of today and tomorrow.

The Office of the CTO is responsible for coordinating EMC's strategy around technology research, both within and across EMC's various product lines and more directly in exploratory research in new technologies. The CTO Office is also responsible for research, concept development, and product development for all of EMC's hardware platforms and systems that are leveraged across EMC's product lines. As leader of the centralized Business Operations and Planning organization within the CTO Office, reporting directly to EMC's CTO, responsibilities include the various business planning and business operation functions across EMC's advanced research and technology exploration, operational execution of the hardware system and platform development activities for the company, and tracking and coordinating EMC's external interactions across both the industry as well as across acedemia.

Global Hardware Engineering is responsible to develop and deliver all hardware platforms for EMC products. As the Director of Operations, I report to the Vice President of Global Hardware Engineering and am responsible for the program management, product release management, engineering services, and environmental product compliance functions within the organization. In addition, I am the organization's primary interface into IT, Finance, HR, and Facilities for execution of projects not core to our hardware platform roadmap but critical for the organization's success.

Responsible for the development and mentoring of the program management staff in EMC's Shanghai Center of Excellence (COE). With dotted-line management responsibility of the program managers in Shanghai, I have visited Shanghai several times for on-the-job mentoring and training. I have also used technology to enhance the team engagement, including telepresence conferences, web camera meetings, and text-based chat. Together with the COE program managers, I am responsible for the delivery of the hardware platforms developed in the COE. I have defined roles and responsibilities such that the COE program managers are the primary focus, with me in a support and mentoring role, enabling the COE team to grow their leadership capabilites through experience. I also have primary responsibility for the interface to our internal customers, as they are in my local time zone. My efforts have enabled true around-the-clock leadership for the programs managed in our COE, and this model has been adopted by other teams within EMC as the one to follow.

Together with an engineering techincal lead in a two-in-the-box matrix environment, I was accountable for the definition, architecture, development, and delivery of new hardware product platforms. Responsible for program management of the hardware program plan, including schedule, requirements, program due diligence, and material resource planning. I was also the key focal point for day-to-day cross-functional communication and planning, bridging the hardware engineering, software engineering, manufacturing, documentation, and external channel partners in order to effectively deliver new products to market.

Responsible for multiple design and verifications teams working both on- and off-shore tasked with design of enterprise-class storage systems, including both board-level and ASIC-level architecture and design. Acted as the center of excellence for hardware engineering's fabric and high-speed interconnect implementations. Continuous interfacing with executive management on project and program status, product roadmap development, translating high-level strategy into specific goals and tasks, and developing talent.

Responsible for a team of design engineers tasked with delivering highly available custom ASIC and FPGA designs, with specific applications in DMA machines, control-plane inter-processor communications, and data protection methods. Using critical-chain project management techniques, maintained project schedules within an overall system schedule, managing both task and resource conflicts in a cross-functional environment to achieve overall system-level schedule optimizations. Converted high-level strategy and schedule needs into day-to-day tasks for the design team.

Designed and verified several custom ASICs, with specific applications in memory management, backplane communications, and error detection and correction.