Christopher Batten Email and Phone Number

Leading a research group of graduate and undergraduate students to explore energy-efficient parallel computer architecture for both high-performance and embedded applications. Using a vertically integrated research methodology that involves rethinking the programming, runtimes, compilers, instruction sets, microarchitecture, and VLSI implementation of future computing systems. Current projects focus on: programmable accelerator-based architectures; general-purpose graphics processing unit (GPGPU) architecture; algorithm and data-structure hardware specialization; architecture and circuit co-design for integrated voltage regulation; and Python-based frameworks to enable more productive computer architecture research methodologies.

Active member of the architecture group which developed new manycore architectures to efficiently integrate hundreds of cores onto a single chip. Reviewer for the patterns group which worked on new design patterns for parallel programming.

Vector-Thread Architectures: Vector-threading (VT) combines the area and energy efficiency of vector architectures with the flexibility of multithreaded execution. Invented new techniques for integrating vector memory accesses into a traditional cache hierarchy. Helped design and implement the Scale VT Processor, a 0.18um ASIC prototype for embedded applications. Our later work studied techniques for simplifying VT architectures through a unified control-/micro-thread instruction set, a microarchitecture based on minimal changes to a standard vector-SIMD implementation, and an explicitly data-parallel C++ programming methodology.Chip-Level Nanophotonic Interconnect Networks: Researched network architectures that leverage monolithic silicon photonics to improve performance and energy-efficiency of on-chip networks, processor-to-DRAM networks, and DRAM memory channel networks. Proposed new physical network layouts that decrease total optical and thermal-tuning power requirements. Implemented a detailed microarchitectural network simulator for performance studies. Collaborated with photonic circuit and device researchers at MIT to both understand the technology as well as influence device design based on system considerations.