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Christopher Ebeling Email & Phone Number

FPGA/RTL Designer
Location: Castle Rock, Colorado, United States 7 work roles 2 schools
1 work email found @tabula.com 1 phone found area 408 LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 86%

Contact Signals · 1 work email · 1 phone

Work email c****@tabula.com
Direct phone (408) ***-****
LinkedIn Profile matched
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Role
FPGA/RTL Designer
Location
Castle Rock, Colorado, United States

Who is Christopher Ebeling? Overview

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Quick answer

Christopher Ebeling is listed as FPGA/RTL Designer based in Castle Rock, Colorado, United States. AeroLeads shows a work email signal at tabula.com, phone signal with area code 408, and a matched LinkedIn profile for Christopher Ebeling.

Christopher Ebeling previously worked as SOC Design Engineer at Intel Corporation and Lead FPGA Designer (Spacecraft) at Planet. Christopher Ebeling holds M.E., Electrical Engineering from University Of Virginia.

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Email format at tabula.com

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{first_initial}{last}@tabula.com
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Profile bio

About Christopher Ebeling

Veteran digital design engineer, with over 30 years of experience in the programmable logic industry, in a wide range of roles, including system architecture, silicon verification, IP development and top tier customer support. Proven ability to innovate and develop solutions to challenges that have no prior precedent. Effective communicator of both technical and feature oriented topics. Enjoys working in a team environment, ability to communicate vision and distribute tasks aligned with individuals interests and skills. Specialties: Verilog, VHDL, all aspects of FPGA design flows. High speed parallel and serial interfaces.PLEASE READ: Attention all recruiters!I am not interested in relocating! I am not currently pursuing a long-term/full time job commitment. If you send me opportunities that don't conform to these restrictions I will not reply!

Listed skills include Verilog, Vhdl, Simulation, Fpga, and 16 others.

7 roles · 43 years

Christopher Ebeling work experience

A career timeline built from the work history available for this profile.

Soc Design Engineer

Santa Clara, California, Us

FPGA architect clocking and memory subsystems.

Mar 2017 - Feb 2019

Lead Fpga Designer (Spacecraft)

San Francisco, California, Us

Oct 2015 - Mar 2017

Distinguished Engineer: Architecture Group

Santa Clara, Ca, Us

Architecture lead for ABAX2P1 memory and clocking subsystems, guided components through all phases of development including eventual verification in silicon. Worked with software group on specification of flow for device initialization and start-up. Mentored members of the application teams on Spacetime friendly design styles, timing closure, and understanding of Spacetime fundamentals.

Jun 2011 - Mar 2015

Principal Engineer (Architecture And Applications)

Santa Clara, Ca, Us

As member of architecture team specified and implemented clock and memory subsystems for Tabula's first generation ABAX device. Drove specification, development, implementation, pre-tapeout verification and eventual verification in silicon of these components. Acted a lead in several early customer engagements with both strategic (feature) and direct technical (Spacetime specific) presentations, engagements and support.

Feb 2007 - May 2011

Principal Engineer Ip Solutions Group

San Jose, Ca, Us

Senior member of the Processing Solutions Group(PSG). Technical lead for Xilinx's SPI-4.2 IP core. Authored specifications a guided team in implementation details for other IP cores.

Dec 2002 - 2007

Staff/Senior Staff Applications Engineer

San Jose, Ca, Us

Supported first tier customers (CISCO, HP, etc) with their FPGA designs, including turn-key design projects. Teamed with software group to integrate Xilinx's EDA tool flow with that NeoCads (acquisition).

Dec 1994 - Nov 2002

Staff Engineer

Ibm

Armonk, New York, Ny, Us

Member of R&D group in IBMs Federal System division, focused on SONAR applications for the US Navy. Implemented memory and interface cards for hydrophone arrays. Pioneered use of FPGA at this site, implemented 8B/10B encode decode functions in Xilinx 3020s. Educated and mentored other engineers at site on proper FPGA design styles.

1984 - Dec 1994
2 education records

Christopher Ebeling education

M.E., Electrical Engineering

University Of Virginia

B.S., Electrical Engineering

University Of Virginia
FAQ

Frequently asked questions about Christopher Ebeling

Quick answers generated from the profile data available on this page.

What is Christopher Ebeling's role at their current company?

Christopher Ebeling is listed as FPGA/RTL Designer.

What is Christopher Ebeling's email address?

AeroLeads has found 1 work email signal at @tabula.com for Christopher Ebeling.

What is Christopher Ebeling's phone number?

AeroLeads has found 1 phone signal(s) with area code 408 for Christopher Ebeling.

Where is Christopher Ebeling based?

Christopher Ebeling is based in Castle Rock, Colorado, United States.

What companies has Christopher Ebeling worked for?

Christopher Ebeling has worked for Intel Corporation, Planet, Tabula, Xilinx, and Ibm.

How can I contact Christopher Ebeling?

You can use AeroLeads to view verified contact signals for Christopher Ebeling, including work email, phone, and LinkedIn data when available.

What schools did Christopher Ebeling attend?

Christopher Ebeling holds M.E., Electrical Engineering from University Of Virginia.

What skills is Christopher Ebeling known for?

Christopher Ebeling is listed with skills including Verilog, Vhdl, Simulation, Fpga, Serdes, Programmable Logic, Xilinx, and Rtl Design.

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