Focused on emulation and verification of networking IP including Ethernet switches, address look up engines (ALE), reassembly engines (RA), and system on a chip (SoC) infrastructure IP including direct memory access (DMA) and queue management (QM).-FPGA emulation, prototyping, and debugging of networking IP using tools from Synplicity, Xilinx, Ixia, and Lauterbach.-Developed application program interfaces (API) in C++ for FPGA test applications.-Developed C++ applications to test functionality of Ethernet switch and direct memoryaccess (DMA) subsystems.-Modified Verilog RTL for FPGA emulation including the design of FIFO monitor RTLand updating of bus interconnect bridge RTL.-Developed the test plan, test applications, and executed the FPGA emulation verificationof the Ethernet switch for Galileo and reassembly engine for Lamarr.-Knowledge and experience in use of networking layers and protocols.-Wrote custom Perl scripts for data manipulation and automation of tasks.-OMAP design for test (DFT) automated test pattern generation (ATPG) for ARM Cortex-A7 using Cadence Encounter Test.

Currently working as a design for test engineer on the OMAP6 platform.

Graduate Teaching Assistant (TA) for computer architecture, capstone, and circuits and sensors.