Christopher Sanchez Email and Phone Number

Roles:Test Pattern/Content Developer, Analog and Mixed Signal IPs (e.g. PCIE, SATA, USB, DP, GBE)Technical Lead Advantest V93K Test Program ConversionsArchitect Test Program Generator tool

Part of the Product Development Engineering (PDE) group working in pre- and post-silicon phases of the product development cycle to drive testability and manufacturability of microprocessor and chipsets silicon designs. Responsibilities include:* Led and managed test program development and qualification for Wafer Sort and Final Test. Led a team of engineers to develop and deliver quality test program.* Managed planning/scheduling of pre- and post-silicon test development activities including definition of yield and test time targets* Managed product cost reduction efforts through test program optimizations (e.g. test time reduction) and test yield improvements to enable faster time-to-market product launch* Drove Wafer Sort and Final Test yield analysis and corrective actions* Drove device characterization activities and report generation* Managed pre-silicon test pattern verification activities* Managed test program deliveries through various phases of pre-production and production ramps* Worked closely with Design Engineers, QnR, Product Engineers, and Test Engineers across sites to establish goals and achieve cross-functional team activities* Led and mentored engineers in the areas of test program development, device H/W board design, device characterization, test time reduction, and QUAL reject verification.Worked on the following products:Tylersburg (Nehalem 5520 Server Chipset), 2006-2009Goldbridge (Intel 6400 Advanced Memory Buffer), 2004-2006Lindenhurst PXH (Xeon 6700 64-Bit PCI-X hub), 2003-2004McKinley (Itanium 2 Server Processor), 1999-2002Mendocino (Celeron Processor), 1998-1999P55C SmartSort (Pentium Die-Level Processor), 1997-1998

Responsible in product startup and High Volume Manufacturing (HVM) support which include monitoring and report of product health indicators (i.e. test yields, bin splits, reject analysis, and other line sustaining activities). Key accomplishments include:* Developed parametric tests (power supply continuity, I/O opens/shorts, leakage, SIDD) and performed hands-on silicon debug. Executed device characterization activities and coordinated test program releases to manufacturing.* Performed yield analysis between Mendocino and Deschutes (feature-identical products) to identify and close yield gap issue between the two.* Reduced system-level testing throughput by 30% with the implementation of a sampling scheme which resulted to increased production capacity.