Chuck Colburn Email & Phone Number

At Home

Austin, Texas Area

Currently leading a small team of engineers responsible for driving performance analysis of Dell's Server-Storage (PERC, Express Flash, and Fluid Cache) solutions. Working with Development teams, Marketing, and Storage Managment to provide data driven analysis of storage workloads to insure best of class storage performanceI have openings for engineers who.

Austin, Texas

• Managed six platforms in the Management phase of the PrP process. Drove all issues (Quality, Field, COS, refreshes) related to the platforms.
• Became the acting DM of two platforms, at the same time, in Deployment Phase when other DMs left Dell.
• While visiting TDC, I became the acting DM of a platform during a Stop Ship.
• Drove the analysis on a mis-processed component that was affecting field quality. Drove the engineering analysis, reported on progress and provided guidance to exec management on possible field exposure.
• Drove the analysis of a DIMM vendors field failure rate that was impacting Client and Enterprise products. Pulled together an across LOB team to drive the vendor in daily calls on the FA of the vendors silicon. Held.
• Managed a team of ~20 engineers world wide in the root cause of a Sev1 issue impacting the RTS of two new server platforms. Gave exec management updates twice each day due to the 24 hour coverage. Engaged with three.

• Providing consulting services in the areas of performance modeling and analysis techniques.
• Developed simulation workload for 1Gig and 10Gig Ethernet products.
• Analyzed the latency of messages over Ethernet using Linux sockets and LAM/MPI.
• Analyzed O/S behavior while using NTttcp, NETPipe, Chariot, and IOMeter as workload generators.
• Configured a system to run SPECsfs for analysis of NFS workload.

Austin, Texas

• Analyzed the performance of K8 and Intel platforms for the Desktop, Workstation, and Server markets.
• Worked with the platform, BIOS, chipset, and processor teams on the debug of any performance issues.
• Generated performance numbers for internal comparison of externally published benchmarks (SPECWeb, SPECCPU, and TPC-C).
• Evaluated early versions of operating systems and compilers supporting x86-64.

Austin, Texas

• Managed multiple teams of engineers responsible for;
• CPU instruction tracing technologies; maintain and enhanced current SpeedTracer tool. Developed a methodology to collect instruction traces from x86 processors. Developed a methodology to collect instruction traces.
• An x86 CPU golden model (SoftCPU) written in C++ used as a functional reference for verification of processor RTL. Drove the development of a full system execution model (Simnow) capable of booting an OS and running.
• System Architectural Model (SAM), a C++ event driven system performance model. Achieved correlation within 5% of a physical system, used in AMD’s decision to support DDR memory rather than RamBus.
• Extensive analysis of 3D graphics and game workloads, AGP memory read latency, and bandwidth on K6/K7.
• Drove first MP memory pattern analysis in AMD, the results were used to aid in the development of an MP Northbridge for K7.

Austin, Texas

• Managed a test engineering team on the Am286LX, an SoC containing a 286 CPU and IBM AT chipset logic.
• Responsible for the tester purchase road map for all of PCD including 386, 486 and 29K products.
• Increased final test capacity on the Am386 by 1.8x by defining a method for dual site test on Teradyne J953 testers.
• Developed real time data collection infrastructure on Teradyne J953 testers at wafer sort and final test. Developed data analysis tools to identify yield issues based on the real time data collection. PCD.
• Managed internal and external engineering teams in the development of an I/O chip for the Diamondback project, an SoC with an integrated 486 for the mobile market. The I/O chip was a PCI device containing IDE, floppy.
• As K5 verification manager coordinated the efforts of five verification teams (44 engineers total). Directly managed three of the teams responsible for; directed test development, verification simulation environment.