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Technical Engineering Manager with a broad based experience in computer and semiconductor industry. Experience in all phases of product development, from product design and test engineering, production, and customer support. Most recent work has been areas of Verification, Software development, and Performance Analysis and Modeling. Known for developing teams of highly motivated engineers.KEY ACCOMPLISHMENTSAt Dell • Drove PERC performace analysis and improvements • Developed DWAT - Dell Workload Analysis Tool • Drove engineering analysis of field exposure for all Enterprise platforms due to a mis-processed component. • Pulled together and managed an across LOB engineering analysis team to find root cause on why one DIMM vendor had a 4x failure rate in the field. • Managed the debug of a Sev1 issue impacting the RTS of two Server platforms and all content in the block release.At AMD • Created and managed a Performance Lab for analyzing K6, K7, K8 and Intel based systems for the Desktop, Workstations, and Servers markets. • Drove the development of a complete system level simulator, written in C++, capable of booting an OS and running applications. Used for pre silicon K7 & K8 BIOS, Compiler, and Operating System development. • Developed and managed the verification methodologies for the K5 microprocessor. Developed a verification environment that achieved over a billion clock cycles per night. • Increased final test capacity on the Am386 by 1.8x to meet production demands.
No Name.Com
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RetiredNo Name.Com Apr 2023 - PresentAt Home
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Server-Storage Advanced EngineeringDell Computer Aug 2007 - Aug 2023Austin, Texas AreaCurrently leading a small team of engineers responsible for driving performance analysis of Dell's Server-Storage (PERC, Express Flash, and Fluid Cache) solutions. Working with Development teams, Marketing, and Storage Managment to provide data driven analysis of storage workloads to insure best of class storage performanceI have openings for engineers who really understand System Arch, RAID, DAS, and SAN performance. -
Manager Tower Csd - Enterprise EngineeringDell Computer Jan 2004 - Aug 2007Austin, Texas• Managed six platforms in the Management phase of the PrP process. Drove all issues (Quality, Field, COS, refreshes) related to the platforms. • Became the acting DM of two platforms, at the same time, in Deployment Phase when other DMs left Dell. • While visiting TDC, I became the acting DM of a platform during a Stop Ship. • Drove the analysis on a mis-processed component that was affecting field quality. Drove the engineering analysis, reported on progress and provided guidance to exec management on possible field exposure. • Drove the analysis of a DIMM vendors field failure rate that was impacting Client and Enterprise products. Pulled together an across LOB team to drive the vendor in daily calls on the FA of the vendors silicon. Held meetings to communicate the current status to broad teams and input to exec updates on a daily basis. • Managed a team of ~20 engineers world wide in the root cause of a Sev1 issue impacting the RTS of two new server platforms. Gave exec management updates twice each day due to the 24 hour coverage. Engaged with three different silicon vendors in root causing the issue. • Was a key part of transitioning ESG-CSD to BDC (Phone screens, on sight interviews, training planning, gap analysis, mentoring BDC managers, acted as local management until exPats and LTA arrived.
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ContractorBanderacom Mar 2003 - Sep 2003• Providing consulting services in the areas of performance modeling and analysis techniques.• Developed simulation workload for 1Gig and 10Gig Ethernet products.• Analyzed the latency of messages over Ethernet using Linux sockets and LAM/MPI.• Analyzed O/S behavior while using NTttcp, NETPipe, Chariot, and IOMeter as workload generators.• Configured a system to run SPECsfs for analysis of NFS workload.
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Manager Performance Architecture And Analysis GroupAdvanced Micro Devices Jan 2001 - Jan 2003Austin, TexasAnalyzed the performance of K8 and Intel platforms for the Desktop, Workstation, and Server markets. • Worked with the platform, BIOS, chipset, and processor teams on the debug of any performance issues. • Generated performance numbers for internal comparison of externally published benchmarks (SPECWeb, SPECCPU, and TPC-C). • Evaluated early versions of operating systems and compilers supporting x86-64. -
Manager Cpu And System AnalysisAmd Jan 1995 - Jan 2001Austin, TexasManaged multiple teams of engineers responsible for; • CPU instruction tracing technologies; maintain and enhanced current SpeedTracer tool. Developed a methodology to collect instruction traces from x86 processors. Developed a methodology to collect instruction traces from MP / Server systems. • An x86 CPU golden model (SoftCPU) written in C++ used as a functional reference for verification of processor RTL. Drove the development of a full system execution model (Simnow) capable of booting an OS and running applications. Used for K7 platform BIOS development and pre silicon K8 BIOS, 64-bit compiler and OS development. • System Architectural Model (SAM), a C++ event driven system performance model. Achieved correlation within 5% of a physical system, used in AMD’s decision to support DDR memory rather than RamBus. • Extensive analysis of 3D graphics and game workloads, AGP memory read latency, and bandwidth on K6/K7. • Drove first MP memory pattern analysis in AMD, the results were used to aid in the development of an MP Northbridge for K7. • Brought up first server workloads, (Serverbench, TPC-C, SPECWeb) on MP K7 systems and worked with BIOS and verification teams to resolve issues. • Developed in-house applications for performance analysis, CATS and ATune a TBS / EBS application. • Managed the Performance Analysis lab, worked with facilities, security, and IT to create a 2000+ sq ft server lab.
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Product Development Manager - Personal Computer DivisionAdvanced Micro Devices Jan 1988 - Jan 1995Austin, Texas• Managed a test engineering team on the Am286LX, an SoC containing a 286 CPU and IBM AT chipset logic. • Responsible for the tester purchase road map for all of PCD including 386, 486 and 29K products. • Increased final test capacity on the Am386 by 1.8x by defining a method for dual site test on Teradyne J953 testers.• Developed real time data collection infrastructure on Teradyne J953 testers at wafer sort and final test. Developed data analysis tools to identify yield issues based on the real time data collection. PCD representative to the Sapphire project, a corporate product-engineering database to support yield and reliability analysis.• Managed internal and external engineering teams in the development of an I/O chip for the Diamondback project, an SoC with an integrated 486 for the mobile market. The I/O chip was a PCI device containing IDE, floppy, power management, RTC, GPIO, and super I/O functionality. Achieved fully functional silicon before being reassigned to the company’s highest priority project, K5.• As K5 verification manager coordinated the efforts of five verification teams (44 engineers total). Directly managed three of the teams responsible for; directed test development, verification simulation environment, and automated test generation tool development (Luther). Luther running on multiple servers and feeding internally built hardware emulators achieved over a billion simulation clocks per night. The directed tests and Luther became the core of the processor verification methodology used on K5, K6, K7, and K8 microprocessors.
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System SpecialistFairchild Test Systems Jan 1979 - May 1980
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Frequently Asked Questions about Chuck Colburn
What company does Chuck Colburn work for?
Chuck Colburn works for No Name.com
What is Chuck Colburn's role at the current company?
Chuck Colburn's current role is Retired.
What is Chuck Colburn's email address?
Chuck Colburn's email address is ch****@****amd.com
What is Chuck Colburn's direct phone number?
Chuck Colburn's direct phone number is (781)-575*****
What schools did Chuck Colburn attend?
Chuck Colburn attended Devry University.
What are some of Chuck Colburn's interests?
Chuck Colburn has interest in Robotics (Hw And Sw), Ray Tracing, Computers, C++ Programming.
What skills is Chuck Colburn known for?
Chuck Colburn has skills like Storage, Debugging, Linux, Hardware, Performance Tuning, Performance Improvement, Testing.
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Chuck Colburn
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Chuck Colburn
Senior Marine Inspector/Flag State Inspector/Outer Continental Shelf Inspector G.O.M At U.S. Coast GuardCovington, La4armor.com, uscg.mil, uscg.mil, uscg.mil
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