Chuck Oliveira Email & Phone Number

Shirley, MA, US

Westboro, MA

* Jasper Formal verification experience with SEC, CC and revCC.* Verification test plan development and scheduling * Verification of Marvell security processors and the familiar with the OpenSSL library* Use of UVM in all of the test bench development.* DDR4 verification using Denali models, UVM and testbuilder.* Full chip simulation verification using C.

• X86 design verification.
• Memory error injections and error recovery
• Branch prediction

* Design verification of audio/video product using SystemC and ModelTech as the simulation plateform

• Designed multiple Xilinx Virtex-4 devices interfacing an internal bus to the industry standard SFI-5 bus running at 2.6 Ghz.
• Design and support for Sonet and G.709 (FEC) frame bus transactors and checkers. These models are written in C++ and interface to verilog via PLI.
• Design and coding of operational and diagnostic code for various line cards.
• Designed various verilog reusable IP such as: Sonet Framer, DPSK encoder and HDLC transceiver.

• Work as group leader or lead technical contributor on most projects.
• Assigned to various client sites for design verification services. This involved test plan development, test script development and simulation verification for ASICs. Devices include FEC, Sonet and Video related designs.
• Design a verification environment for a Forward Error Correction (FEC) ASIC used in telecommunications. The test bench and behavioral models for this ASIC were written in Verilog and C/PLI

• Design verification of a color correction ASIC used in the video industry. The test bench and behavioral models for this ASIC were designed using C++. Design PERL scripts to automate the comparison of RTL and.

• Co designer for an ASIC that incorporated major functions of a cardiac ultrasound machine. Also responsible for tools selection and device design verification. This ASIC was a success on first pass silicon.
• Division Synopsys synthesis engineer. Responsible for synthesis design services within and across divisions. Synthesis was performed on new ASICs as well as old ASICs that were being re-spun due to ‘last time’ purchases.
• Support and training for design verification tools. This required Unix system support, installation, setting up scripts and testing of new tools.

Master Of Computer Science, Data Science And Ml, 3.85/4.0

Bsee, Electronics