Chuck Wilde (Will'-Dee) Email & Phone Number

Naperville

Team leader of the FPGA designers, part of the engineering design services team developing proof of concept, prototype and production systems for contract manufacturing customers. Work is done in the fields of medical devices, aerospace, and industrial applications.

Naperville, IL

Part of the Design Services organization for Contract Manufacturer OnCore. Current position has me developing Verilog code for an FPGA as part of a small team.

To Paraphrase Philip Nolan, I Am An Engineer Without A company.

Targeting a position in digital device design or C/C++/Perl programming, where I can apply my experience and expertise toward the solution of complex problems.Looking for positions in the greater Chicagoland area, or the Front Range in Colorado.

• Part of a 7 member team that analyzed circuit board designs from multiple ALU sites in 5 countries for signal integrity and power integrity. Valuable resource for developing tools for process improvements.
• Analyzed 12+ designs for SI (DDR3, Serdes, Clocks) and 2 designs for PI. Documented violations and offered solutions to the circuit board designers, avoiding potential board changes.
• Pioneered use of DDRx Wizard feature in Mentor HyperLynx and instructed team in its use. As a result, Wizard was adopted for DDR3 interfaces, reducing analysis time per interface from 3 days to ½ day.
• Developed common IBIS library for team, reducing preparation time required for each new analysis. Updated Perl script to add IBIS keywords and timing data to models, reducing number of false SI violations.
• Created suite of Perl scripts to analyze hundreds of large Excel spreadsheets for circuit board reliability data that enabled co-worker to generate required reports on schedule.

• Developed digital devices for internal products, working both individually and as part of multi-person teams. Installed and maintained design tools.
• Implemented 10+ designs in Altera, Xilinx FPGAs. Started with system requirements, coded in VHDL and verified via code reviews and functional simulation, developed test plan and test programs for verification in.
• Took ownership for TCP/IP and Serial RapidIO (sRIO) interfaces on 2 separate FPGA design projects when design team had no expertise. Accessed reference materials, ALU experts and FPGA vendor resources to develop.
• Redesigned 10+ ASIC designs for cost reduction or End Of Life issues. Saved over $5 Million in lower device costs and avoidance of Last Time Buys, while also keeping factory supplied with needed devices.
• Developed 12+ functional verification testbenches in VHDL and Verilog. Increased productivity by accelerating verification phase of device design, providing >95% coverage of functional requirements.
• Administered external ASIC and FPGA design tools (Synthesis, Verification, Place&Route), maintaining matrix of Solaris and Linux design environments. Supported up to 20 simultaneous designers and 50+ projects.

• Developed/maintained internal CAE tool for displaying simulation waveforms. Served as customer support representative for AT&T location in Denver, CO.
• Reduced size of the waveform file 80% using compression algorithm. Limited number of times designers ran out of storage space.
• Monitored trouble tickets from Denver location, advocated for site with tool developers. Closed numerous trouble tickets.

Ms, Electrical Engineering

Activities and Societies: College Bowl team, College Bowling team

Bs, Electrical Engineering

Activities and Societies: Lambda Chi Alpha, Jazz Band

Interior Design, Kitchen And Bath Design, Mandarin Chinese

Education record