Working on Synopsys ARC NPX6 NPU compiler backend.

Working on improving the performance and scalability of Prescan distributed sensor simulation.

Working on Prescan distributed sensor simulation and real-time platforms.

Working on PreScan, a physics-based simulation platform that is used in the automotive industry for development of Advanced Driver Assistance Systems (ADAS) that are based on sensor technologies such as radar, laser/lidar, camera and GPS.Currently work on physics based camera project, focusing on improving simulation performance using:- Physics based rendering- OpenSceneGraph, OpenGL- GPU-accelerated simulation: distributed rendering (multi-GPU/cluster), OpenCL

Architecting and developing GPU memory access optimizations in the European Commission FP7 ENCORE project. - Runtime memory access pattern/locality analysis for GPU CUDA kernels; - Microarchitectural techniques (e.g., smart caching/prefetching) to reduce off-core/chip memory access bandwidth/latency and improve memory-level parallelism, by exploiting GPU memory access patterns and data locality.

Phd Candidate at the Computer Engineering (CE) Lab under the guidance of Prof. Georgi N. Gaydadjiev. Worked on the European Commission FP6 SARC project.Independent research on employing system-level solutions (cross compiler/runtime/architecture boundaries) to improve memory efficiency and processor performance for contemporary data parallel architectures. Published 2 journal and 4 conference papers in prestigious international venues, including a Best Paper Award in ACM International Conference on Supercomputing (ICS, among top 5% in all computer science conferences).- Analyzed SIMD data rearrangement overhead, designed multi-bank, conflict-free memory to eliminate the overhead for common data access patterns, and integrated it to an IBM Cell processor model as a multi-view memory. Provided API to allow the programmer to express data views, and modified gcc SPU backend to generate new instructions to allow conflict-free memory accesses;- Analyzed GPGPU kernel performance degradation caused by GPU shader core scratchpad memory bank conflicts. Designed Elastic Pipeline to enhance the core pipeline by reducing pipe stalls due to bank conflicts;- Analyzed data locality among GPU parallel threads' execution, developed CPU runtime to analyze the GPU kernel code to extract the locality, and designed a smart GPU shader cache to exploit the available locality;- Had fun with writing small tools to automate my simulation/design flows.

Research Assistant at Institute of High-Speed Signal Processing, Department of Electronic Engineering. Developed a Synthetic Aperture Radar (SAR) signal emulation system.- Architected a real-time signal processing PCI board employing dual TI DSPs and Altera FPGAs with double buffering;- Developed the PCB schematic, designed the FPGA RTL logic, wrote the DSP signal processing kernel code and host PCI driver and control software;- Brought up the SAR signal emulation system, and performed field testing together with colleagues for an airborne SAR at Yanliang, Shanxi, China.

Interned with TD-Tech, a Siemens-Huawei company. Contributed to TD-SCDMA NodeB upgrade from LCR 1.0 to 2.0, which doubles the base station mobile call processing capacity.- Developed RTL code for IQMUX FPGA, which provides ultra-high speed data path between the SIPROC (baseband signal processing module) and the RFTRXU (RF transceiver module) in TD-SCDMA baseband processing node;- Participated in TD-SCDMA NodeB LCR 2.0 system bring-up. Captured and solved system hardware bugs.