• RTL design, integration, release to production for 10+ rtl to silicon cycles• Responsible for the SAS phy, link, and port layer modules, as well as the SATA link layer modules across the division’s four different product lines (2010-)• Coordinate with off-site RTL design teams to design features that cross multiple blocks (2010-)• Proposed to clients a proprietary protocol which allows legacy SAS devices to linkup across optical cables. Defined requirements, designed protocol, and architected the firmware sequence. Led off-site development effort to bring the feature to production. The feature is being rolled out across 3 product lines. Patent Pending (2012-2013)• Designed a custom SATA link up sequence extension which provides extra time for analog tuning. Defined the modifications and implemented in RTL (2010)• Extended specman simulation testbench for SAS low power support. Wrote e testcases. (2009-2010); Collaborate with verification team to develop test plan for new RTL features. Review Simvision simulation waveform results (2010-)• Provide domain knowledge and support, including lab debug, to validation, firmware, and application teams for multiple generations of chips, approximately 24 products overall. Lab tools used include JDSU XGIG and LeCroy SAS analyzer, Xilinx ChipScope capture and waveform viewer (2010-)• Set up Cadence Conformal CDC environment and performed checks (2011); Review Meridian CDC setup and checks• Worked closely with DFT, synthesis, STA, and layout teams; Reviewed logs, defined SDC timing constraints, wrote post-layout ECO scripts, and created PHY-specific STA scripts for interface timing measurement (2009-)• Presented training sessions to team members about the SAS protocol and new features (2010-)• Received 3 internal awards for innovation, customer service, and dedication respectively

Completed a Master's degree with research focusing on synthetic stochastic system on chip benchmark circuits for FPGA architecture research.