Cindy Tseng Email & Phone Number

Pushed out next generation power management features in servers. Left to complete masters in data science

Presented work in bias in deep learning models in Strata 2019 San Francisco conference; Researched papers in bias reduction deep learning models and conducted experiment to measure bias amplification on computer vision models with biased autonomous driving data. Contributed to Intel’s Ethical AI technical guide.Various Linux environment setup work to get caffe and tensorflow GPU working. Left due to project cancellation

Technical Lead for miscellaneous (MSC) block in deep learning hardware accelerator project. Drove features in power management, thermal management, security, and reset on a chip consisting both Intel protocol compliant IP and industry standard protocol compliant 3rd party IP. Design micro-architecture while taking into account security implications, reset flow, firmware interactions, validation and backend costLeft to work in a different field

Precognition of Falls in the Elderly wearable project (IOT). Developed wearable remote data collection proof of concept using Feather microcontroller. The wearable aims to open a $4.2 Billion elderly market to Intel by 2021, with 16.9 Million recurring customers in the developed world

Architected micro-architecture changes required to make memory controller from one project compatible with phy layer from another project. This involved translating KTI to SMI protocolsProjected schedule impact on memory controller feature changes

Helped define microarchitecture reset for future knights projectOversaw logic quality work at SoC. Helped come up with SoC logic quality metric to ensure high quality Sillicon and negotiated deliverable for each milestone. Improved SOC integration efficiency by adding automated processes. Such as mesh latch repeaters insertion, logic quality review etc. Some of the process is reused in emulation and other projects.

Drove architecture definition and RTL implementation for global fabrics. These include message channel, pmlilnk, fuselink, reset sequence. There was zero bug in these global fabrics in silicon. Represented memory controller team and helped with A0 power on

Root-caused several PRQ and RPT gating bugs related to power, RAS etc. Came up with workarounds in post-Si and helped Intel saved millions of dollars by avoiding an extra extra steppingPerformed manual netlist edit using Synopsis IC compiler with 200+ gate edits using ICC scripts to ensure minimal netlist change compared to using automated synthesis. This resulted in on time tape out with late bug fixes.Implemented key features in scheduler in memory controller that interacts with DDR4 and MCDRAM memory devices. These include scheduling commands that comprised with memory device timing requirements, retry commands, catch up on refreshes, and log link errors and interrupt generationWorked with RAS architects to close on gaps and correct errors in RAS specification. Owned features such as categorizes, logs, and reports errors. ECC checking, error injection Data poisoning, corruption propagation Demand scrub, patrol scrubRow hammer, and data scramblingPower management feature in memory controller, resulting in ~10% power reduction.Thermal management feature in memory controller that controls bandwidth throttling.Worked with memory controller validation to ensure all cases were covered.Created memory controller micro-architecture slide and held memory controller training sessions for fullchip team to enable validation in global features.Evaluated all cross clock domain signals in memory controller to ensure they are handled correctly.

Worked on validating thermal management unit. Enhanced reference model that mimics the different stimulus that triggered thermal management. Exercised test under usual and corner cases.Enhanced I2C reference model. Wrote tests for cluster testing use. Also helped fullchip, high volume testing team, and post silicon team on developing their I2C and thermal management test.Main contributor to fan speed controller reference model. Developed design for testing test for cross functional unit teams.Enhanced and reviewed test plans for thermal management features.

Worked in display controller team. Helped debug existing test suits.

Santa Clara, California, Us

Worked in display controller team. Helped debug existing test suits.

Santa Clara, California, Us

Helped solve critical speed paths by making schematic changes and planning implementation of layout

Master'S Degree, Data Science

Masters, Electrical And Computer Engineering

Bachelor Of Engineering - Be, Electrical Engineering

Education record