Cliff Lee Email & Phone Number

• Silicon-package-system co-design for Azure high performance computing data center products (Cobalt, Maia).
• Led team to architect/design/tapeout SOC packages for Azure silicon products.
• Silicon floorplan architecture optimization for system IO and package technology.
• IC package fabrication and assembly design rules roadmap development with manufacturing factories.
• Drove advanced signal/power integrity designs for IC packaging.
• Defined test chips/interposers/substrates to innovate 2.5D/3D package technologies.

• Cryogenic interconnect technology for a future generation network Backplane.
• Superconducting substrate process thin-film deposition (Niobium, Polyimide, Molybdenum)
• End-to-end network topology Backplane signal integrity analysis on Single Flux Quantum logic.
• Defined Backplane technical architecture of a 600-node network using Dragonfly+ topology.
• High Temp Superconductor (YBCO) flexible RF interconnect development 4K-233K temp zones
• Cryogenic connector development for Backplane and flexes interconnect

Redmond, WA

• Led Microsoft Surface/Xbox/Hololens Devices PCB & FPC Technology Roadmap
• SME for PCB and FPC manufacturing and design rules
• Author Microsoft PCB manufacturing spec, PCB/FPC process design rules
• Coach product team cost-effective PCB/FPC EE designs
• Managed 14+ PCB/FPC suppliers in Asia to develop new technologies for Microsoft
• Drove PCB & FPC supplier strategy and business development

Hillsboro, OR

• Built a world-class IC package engineering org to design CPU packages for Intel’s Core i7/i5/i3
• Responsible to manage 80+ successful production CPU package designs tapeout
• Led CPU package pinmap definitions, signal/power integrity
• Org efficiency by merging mobile and desktop CPU packaging org
• People development to build org core-competency and cross-functional design disciplines
• Set CPU packaging roadmap to support Intel Core/Atom CPU products

Hillsboro, OR

• Managed EE team to deliver electrical specification PCI Express Gen1/Gen2
• Built org core-competency on platform signal integrity
• Led PCI Express Gen1 electrical design team and author of PCIe platform design guide
• Contributing author for PCI Express 1.0 Specification and Card Electro-mechanical Specification
• Represented Intel in PCI-SIG industry forums as expert speaker for PCI Express Platform designs

Hillsboro, OR

• Led signal integrity team to deliver Front-side bus and DDR-400 for Xbox 1st generation
• Led electrical analysis team to deliver AGP8x electrical interface specification
• Co-author for AGP3.0 Spec (v1.0) and Design Guide (v1.5)
• Led PC hardware team to design smallest PC platform based on Intel’s Timna
• Led engineering team to design Rambus memory module (RIMM) for Intel’s Timna CPU
• Architect S-RIMM (SDRAM-to-Rambus) memory module development with suppliers

Hillsboro, OR

• Led engineering team to design desktop platform for Intel’s Pentium II CPU
• Designed Pentium/Xpress/EISA server platform to boot DOS, Windows, Unix system validation

Hillsboro, OR

• Designed motherboard for Intel’s Pentium Pro processor and PCI chipset for Server EISA platform
• Designed full system-level VHDL simulation test benches for CPU/chipset models for pre-silicon validations

M.Eng., Electrical And Computer Engineering

Bsee, Electrical Engineering