Iteratively laid out multiple AMS (analog/mixed signal) I/O libraries, including receivers, transmitters, power/ground cells, bank termination cells, corner cells, and full I/O rings, in 0.18 uM bulk, cmos90 bulk, cmos90 soi, cmos65 bulk , cmos65 soi, cmos45 bulk, cmos45 soi, cmos32 soi, cmos28 bulk, and 16nM FinFET technologies.Programmed pcells (parameterized cells) for automated, correct-by-construction layout of ESD-specific devices (transistors, diodes) in FinFET, Bulk, and SOI technologies.Supported ESD (electro-static discharge) and latch-up protection process development efforts across multiple generations of semiconductor products.Participated in analog design teams to layout operational amplifiers, phase locked loops, temperature sensors, ring oscillators, voltage references, decoupling capacitors, MIM capacitors, etc. for networking processors.Created scribe grid test structures for both standard and novel devices for characterization and to enable creation of intellectual property across multiple new technology nodes in FinFET, Bulk, and SOI technologies.Created QA (quality assurance) cells to enable design rule checking (DRC and ERC) and “pipe clean” early PDK releases in multiple technology nodes.Created ESD- and latch up-specific standard cells to augment foundry and third party offerings in FinFET, Bulk, and SOI technologies.

Characterized wafer level devices and circuits for ESD performance targets and research and developmentBuilt and automated Motorola's first Transmission Line Pulse ESD tester