Senior Electrical Engineer with wide range of experience in ASIC & FPGA design. Knowledge covers design planning, architecture, documentation, implementation, verification, synthesis, floorplanning, timing closure/analysis, integration, testing, and debug.Specialties: • Strong knowledge of Fastscan, TestKompress, Microsoft Office (including Project and Visio), Questasim, Spice, Synopsys Design Compiler, Synopsys Primetime, Spyglass, Clearcase, Magma, Quartus, and Subversion.• Experience with assembly code, C, FORTRAN, MATLAB, Perl, TCL/TK, Verilog, and VHDL.• Familiarity with DOS, Linux, UNIX, Macintosh, and Windows.
Listed skills include Tcl, Verilog, Vhdl, Clearcase, and 4 others.