Clyde R. Visser, P.E. Email & Phone Number

Irvine, CA, US

Vhdl / Rtl / Fpga designer

North Andover, MA, US

Remote contractor and member of development and verification teams for satellite test beds and RISC-V based secure computing platforms. Design verification aided of next generation ASIC using Xilinx UltraScale+ FPGAs. Design work for satellite module testing platform using Axi Streaming interface of event detection and accumulation for query by multiple.

Melbourne, Florida, US

Responsible for architectural design and evaluation of effectiveness of side channel attack mitigation techniques used to protect block cipher encryption algorithms for use in the next generation GPS ASIC. Familiarity with ChipWhisperer hardware & software tools to evaluate side channel attack techniques and measure effectiveness of various mitigation.

Arlington, VA, US

Responsible for support and sustaining existing Xilinx FPGA based avionics control subsystems.

Irvine, CA, US

UC Irvine Extension Instructor in the courses of Embedded System Architecture and VHDL Design and Modeling of Digital Systems of the Embedded Systems Engineering certificate program and Digital Signal Processing with FPGA's of the DSP Systems Engineering certificate program. Incorporated the use of the Digilent Atlys™ Spartan-6 LX45 FPGA Development Board.

Responsible for support and maintenance of way-side FPGA based sub-systems used in successful early HyperLoop prototype. Implemented ADC IPs supporting multiple devices using I2C & SPI interfaces on MicroZed 7010/20 development boards. Also implemented Pwm H-bridge multi-level drive IP and 8B/10B communications IP used in a counter-rotating ring topology.

Andover, MA, US

Responsible for design and implementation Pipelined DSP algorithms using a Xilinx Virtex-7 XC7VX485T FPGA with FPGA Mezzanine Card (FMC) technology. Modified C/C++ code in Visual Studio Express IDE to interface to 4DSP high speed (5GSPS) ADC and DAC technologies. Implemented AES-GCM and AES-XTS 256-bit key encryption, decryption, and authentication logic.

Houston, Texas, US

Responsible for the design and implementation of the Pantera twelve phase eight megawatt motor drive embedded control system electronics using National Instruments CompactRIO technologies. Drive control implemented Volts/Hertz and vector control (field-oriented control (FOC)) modes within LabVIEW FPGA. Took courses in Fundamentals of LabVIEW, Intermediate.

New York, NY, US

Responsible for lead technical design, implementation, test and integration of the digital control electronics for various power conversion systems and motor drives for commercial and military applications. The hardware designs utilized TMS320C6711 & TMS320C6713 floating point DSPs and Xilinx Spartan-3, Virtex-II, & Virtex-4 FPGAs. Communication.

Irvine, California, US

Responsible for engineering enhancement and cost reduction of the cNode 2010 and cNode 2020 internet protocol measurement device product lines. Performed signal integrity and electromagnetic compatibility (EMC) analysis using Hyperlynx BoardSim. 10/100BASE-T Ethernet, GPS, MIPS, PCI. Contributed to internal architecture and time synchronization design..

New York, NY, US

Responsible for design, implementation, test and integration of the digital control electronics of the ACFC150, a 150 kilowatt 60Hz to 400Hz air cooled frequency power converter. The design utilized multiple TMS320F240 DSPs and Xilinx Spartan 30K gate FPGAs. Wrote DSP control code in C and assembly. Designed FPGAs in VHDL, LogiBLOX, and schematic using.

US

Responsible for development of the Asynchronous Transmission Mode (ATM) quality of service measurement portion of the Vista ATM product line. The electronics utilized multiple ADSP-2171 DSPs and Xilinx FPGAs. Designed using multiple Xilinx and Lattice FPGAs. Software experience included Linux, Venix, and X-Windows. Programmed in ADSP-2171 DSP assembly.

Responsible for the design and implementation of the control electronics for the Bear 1000 Critical Care Ventilator product line. The electronics utilized I80188 CPU and 68HC705C8 MCU, switch mode power conversion, and stepper motor control. Used P-CAD schematic capture to design hardware. Used PALASM HDL on Programmable Logic Devices (PLD).

Software engineering supervision of a team of engineers responsible for the System Manager portion of the DS-512 Digital Automatic Call Distributor (DACD) product. Design specification and implementation for system Real Time Display which supported 24 terminals. Responsible for specification, design, and implementation of both hardware and software for an.

Bsee, Digital Emphasis

Specialized Studies Award, Advanced Digital Systems Engineering