Clyde R. Visser, P.E. Email and Phone Number
Clyde R. Visser, P.E. work email
- Valid
- Valid
- Valid
- Valid
Clyde R. Visser, P.E. personal email
Clyde R. Visser, P.E. phone numbers
Extensive experience in system level design of cryptography, data communication, telecommunication, medical life support, power conversion, and motor drive products. Processor hardware design engineering with fixed & floating point digital signal processors (DSP) and RISC-V & ARM Cortex-A9 central processing units (CPU). Further hardware design includes AES block cipher cryptography, state machines, system on a chip (SoC), field programmable gate arrays (FPGA), PCI and VME bus interfacing, dynamic memory control, and switch mode power conversion. FPGA designs included Digital Signal Processing (DSP), soft-core and hard-core processors, 8B/10B encoder / decoders, SCR / IGBT power electronics control drives, High-speed ADC & DAC signal processing, PCI interfacing, and Direct Digital Synthesis (DDS). Software engineering in C and assembly language for ARM Cortex-A9, TMS320 fixed point DSPs, and MicroBlaze CPU families and LabVIEW for RTC and FPGA environments. Cryptographic code implementation of AES / Rijndael block ciphers for various operation modes (XTS, GCM, ECB etc) and various BitCoin functions necessary for the creation of a BTC miner in VHDL. Implemented and measured effectiveness of various anti-tamper techniques protecting block ciphers. Project supervision of an engineering design team. Software design for embedded real time control of avionics, telecommunications, medical life-support, power conversion systems, and motor drive products. Computer aided design with Orcad and P-CAD schematic capture software packages. FPGA development platforms for ModelSim, Xilinx (ISE & Vivado), Altera (Quartus II & Qsys), and MicroSemi/Actel Libero. Signal integrity (SI) and electromagnetic compatibility (EMC) analysis using Hyperlynx BoardSim. Programmable logic design experience in VHDL, Verilog, and SystemVerilog hardware description languages (HDL) RTL. VRTX real time operating system (RTOS). Data communication experience with PCIe, Fibre Channel, Low-Voltage Differential Signaling (LVDS), and Ethernet. Extensive teaching experience in both face-to-face and online instructional environments of embedded systems and FPGA design subject matter courses.
-
Principal Firmware (Fpga) Engineer, IvIris Technology Oct 2023 - PresentIrvine, Ca, Us
-
Vhdl GuruExpertronix Jan 2000 - PresentVhdl / Rtl / Fpga designer
-
Sr. Design EngineerParadigm Works, Inc. Oct 2021 - Jul 2023North Andover, Ma, UsRemote contractor and member of development and verification teams for satellite test beds and RISC-V based secure computing platforms. Design verification aided of next generation ASIC using Xilinx UltraScale+ FPGAs. Design work for satellite module testing platform using Axi Streaming interface of event detection and accumulation for query by multiple soft-core MicroBlaze processors. Wrote low level interface code in C++ to process said accumulations. Vivado project file generation using TCL. Project code and testbench code revision using SVN & Git. -
E5 Lead EngineerL3Harris Technologies Mar 2019 - Oct 2021Melbourne, Florida, UsResponsible for architectural design and evaluation of effectiveness of side channel attack mitigation techniques used to protect block cipher encryption algorithms for use in the next generation GPS ASIC. Familiarity with ChipWhisperer hardware & software tools to evaluate side channel attack techniques and measure effectiveness of various mitigation techniques. Training in Airborne Electronic Hardware (DO-254) from Patmos Engineering Services. -
Principal Electrical EngineerRaytheon Jun 2018 - Mar 2019Arlington, Va, UsResponsible for support and sustaining existing Xilinx FPGA based avionics control subsystems. -
Continuing Education InstructorUc Irvine Apr 2005 - Jun 2018Irvine, Ca, UsUC Irvine Extension Instructor in the courses of Embedded System Architecture and VHDL Design and Modeling of Digital Systems of the Embedded Systems Engineering certificate program and Digital Signal Processing with FPGA's of the DSP Systems Engineering certificate program. Incorporated the use of the Digilent Atlys™ Spartan-6 LX45 FPGA Development Board and ZYBO Zynq™-7000 Development Board, Xilinx Vivado and ISE Design Suite and Mentor Graphics ModelSim ASIC and FPGA Design Simulator tools into the VHDL and DSP courses for hands-on learning experience of various design topics. Developed the online courses using the Moodle open-source Learning Management System (LMS). Instructed hundreds of students in both on-line and face-to-face environments. -
Senior Advanced Embedded Systems EngineerHyperloop One Nov 2016 - Apr 2018Responsible for support and maintenance of way-side FPGA based sub-systems used in successful early HyperLoop prototype. Implemented ADC IPs supporting multiple devices using I2C & SPI interfaces on MicroZed 7010/20 development boards. Also implemented Pwm H-bridge multi-level drive IP and 8B/10B communications IP used in a counter-rotating ring topology on Xilinx Zynq-7000 SoC ZC706 XC7Z045 SoC/FPGA. IP code was implemented using VHDL, Verilog, and SystemVerilog. Also used source code revision tool git for code development.
-
Senior Electronics EngineerPhysical Optics Corporation Aug 2013 - Nov 2016Andover, Ma, UsResponsible for design and implementation Pipelined DSP algorithms using a Xilinx Virtex-7 XC7VX485T FPGA with FPGA Mezzanine Card (FMC) technology. Modified C/C++ code in Visual Studio Express IDE to interface to 4DSP high speed (5GSPS) ADC and DAC technologies. Implemented AES-GCM and AES-XTS 256-bit key encryption, decryption, and authentication logic in Actel/MicroSemi IGLOO nano 250K-gate and ProASIC3E 1.5M-gate FPGAs, Altera Cyclone V SoC, and Xilinx Zynq SoC devices. Implemented slave and streaming interfaces for Altera Avalon and ARM AXI-4 buses. -
Sr. Digital EngineerFmc Technologies Feb 2011 - May 2013Houston, Texas, UsResponsible for the design and implementation of the Pantera twelve phase eight megawatt motor drive embedded control system electronics using National Instruments CompactRIO technologies. Drive control implemented Volts/Hertz and vector control (field-oriented control (FOC)) modes within LabVIEW FPGA. Took courses in Fundamentals of LabVIEW, Intermediate LabVIEW, LabVIEW Connectivity, LabView FPGA. Obtained Certified LabVIEW Associate Developer (CLAD) certificate. -
Principal Digital EngineerL-3 Communications Mar 2002 - Feb 2011New York, Ny, UsResponsible for lead technical design, implementation, test and integration of the digital control electronics for various power conversion systems and motor drives for commercial and military applications. The hardware designs utilized TMS320C6711 & TMS320C6713 floating point DSPs and Xilinx Spartan-3, Virtex-II, & Virtex-4 FPGAs. Communication technologies used included RS-485, LVDS, & Fibre Channel. Bus standards used included VME & PCI. FPGA technologies used included Rocket I/O Multi-Gigabit Transceiver (MGT), Xesium Clock Technology, & MicroBlaze. -
Sr. Digital EngineerCqos Jun 2000 - Mar 2002Irvine, California, UsResponsible for engineering enhancement and cost reduction of the cNode 2010 and cNode 2020 internet protocol measurement device product lines. Performed signal integrity and electromagnetic compatibility (EMC) analysis using Hyperlynx BoardSim. 10/100BASE-T Ethernet, GPS, MIPS, PCI. Contributed to internal architecture and time synchronization design. Maintained and modified Xilinx Spartan II 150K gate FPGA code and Xilinx Virtex 109K gate FPGA code. -
Sr. Digital Hardware EngineerL-3 Communications Apr 1997 - May 2000New York, Ny, UsResponsible for design, implementation, test and integration of the digital control electronics of the ACFC150, a 150 kilowatt 60Hz to 400Hz air cooled frequency power converter. The design utilized multiple TMS320F240 DSPs and Xilinx Spartan 30K gate FPGAs. Wrote DSP control code in C and assembly. Designed FPGAs in VHDL, LogiBLOX, and schematic using Xilinx Foundation Series software. Designed VME back planes using offset strip-lines and embedded micro-strips for controlling characteristic impedances.
-
Sr. Digital EngineerAmeritec Corporation Feb 1991 - Apr 1997UsResponsible for development of the Asynchronous Transmission Mode (ATM) quality of service measurement portion of the Vista ATM product line. The electronics utilized multiple ADSP-2171 DSPs and Xilinx FPGAs. Designed using multiple Xilinx and Lattice FPGAs. Software experience included Linux, Venix, and X-Windows. Programmed in ADSP-2171 DSP assembly language. Used Orcad schematic capture for Xilinx FPGAs. Responsible for the product enhancement, cost reduction, and EMC FCC certification of the NetWatch product line. The electronics utilized a MC68000 CPU and TMS320C10 DSP. Also implemented Dataphone Digital Service (DDS) telecom interface using multiple Xilinx FPGAs. Designed with switched capacitor anti-aliasing filter using FilterCAD (FCAD) from Linear Technology. Used Tango schematic capture and ABEL HDL for FPGA design. -
Sr. Digital EngineerViasys Healthcare Mar 1988 - Feb 1991Responsible for the design and implementation of the control electronics for the Bear 1000 Critical Care Ventilator product line. The electronics utilized I80188 CPU and 68HC705C8 MCU, switch mode power conversion, and stepper motor control. Used P-CAD schematic capture to design hardware. Used PALASM HDL on Programmable Logic Devices (PLD).
-
Sr. Digital EngineerQualitel Services Aug 1985 - Feb 1988Software engineering supervision of a team of engineers responsible for the System Manager portion of the DS-512 Digital Automatic Call Distributor (DACD) product. Design specification and implementation for system Real Time Display which supported 24 terminals. Responsible for specification, design, and implementation of both hardware and software for an audio services processor module. The module used a TMS320C25 DSP, programmable logic state machines. Software design in TMS320C25 assembly and MC68010 ‘C’ and assembly code utilizing a VRTX RTOS. The module performed all of the audio services (such as tone detection and generation, voice record and playback, and conferencing functions) for the DS-512 Digital Automatic Call Distributor (DACD) product.
Clyde R. Visser, P.E. Skills
Clyde R. Visser, P.E. Education Details
-
California State Polytechnic University-PomonaDigital Emphasis -
Uc IrvineAdvanced Digital Systems Engineering
Frequently Asked Questions about Clyde R. Visser, P.E.
What company does Clyde R. Visser, P.E. work for?
Clyde R. Visser, P.E. works for Iris Technology
What is Clyde R. Visser, P.E.'s role at the current company?
Clyde R. Visser, P.E.'s current role is Principal Firmware (FPGA) Engineer, IV at Iris Technology.
What is Clyde R. Visser, P.E.'s email address?
Clyde R. Visser, P.E.'s email address is el****@****zon.net
What is Clyde R. Visser, P.E.'s direct phone number?
Clyde R. Visser, P.E.'s direct phone number is +121380*****
What schools did Clyde R. Visser, P.E. attend?
Clyde R. Visser, P.E. attended California State Polytechnic University-Pomona, Uc Irvine.
What skills is Clyde R. Visser, P.E. known for?
Clyde R. Visser, P.E. has skills like Embedded Systems, Fpga, Embedded Software, Digital Signal Processors, Firmware, Electronics, Vhdl, Hardware Architecture, Systems Engineering, C, Microcontrollers, Electrical Engineering.
Free Chrome Extension
Find emails, phones & company data instantly
Aero Online
Your AI prospecting assistant
Select data to include:
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial