President/Principal Engineer
Current• Validated the Paneve processor models (SystemC/RTL/FPGA/reference) against each other. Managed regressions and wrote custom regression/automation/analysis utilities as needed. Specifiied new randomized test generation algorithms/targets for implementation. • Root-caused bugs, and traced to design changes, software/compiler changes, tool/OS/platform changes, &c (semi-automated fast diagnosis so bugs are fixed when cheap to fix). Helped create metrics to assess quality and coverage.. Managed others in related roles and mentored interns.• Automated clean compiler builds and debugged builds. • Reviewed and improved client verification plan, incorporated random test requirements,. • Introduced TestBuilder (pre-SystemC) as an efficient new testbench methodology for storage client, other best-in-class techniques.• Developed TestBuilder (pre-SystemC) testbench for client's 5M-gate chip, tested, incorporated new designer requirements, reported issues with chip.• Established fully automated nightly regressions with automatic success/fail reporting for subsystem level tests, leveragng unused nightly client compute and license resources. Very useful in daily status meetings for identifying newly broken subsystem features that could then be easily backed out or fixed.• Helped define and develop industry-standard test plan for client's initial FPGA implementation; collected requirements from designers/spec, prioritized with design team input.• Initial code coverage data collection and analysis, worked with designers to see if holes could/should be addressed.• First to prototype a simulation connecting all subsystems in simulator to exercise simple functionality, before feasible in lab.• Received client's “Thank You” award for verification of high-profile 5M gate ASIC.
