• Validated the Paneve processor models (SystemC/RTL/FPGA/reference) against each other. Managed regressions and wrote custom regression/automation/analysis utilities as needed. Specifiied new randomized test generation algorithms/targets for implementation. • Root-caused bugs, and traced to design changes, software/compiler changes, tool/OS/platform changes, &c (semi-automated fast diagnosis so bugs are fixed when cheap to fix). Helped create metrics to assess quality and coverage.. Managed others in related roles and mentored interns.• Automated clean compiler builds and debugged builds. • Reviewed and improved client verification plan, incorporated random test requirements,. • Introduced TestBuilder (pre-SystemC) as an efficient new testbench methodology for storage client, other best-in-class techniques.• Developed TestBuilder (pre-SystemC) testbench for client's 5M-gate chip, tested, incorporated new designer requirements, reported issues with chip.• Established fully automated nightly regressions with automatic success/fail reporting for subsystem level tests, leveragng unused nightly client compute and license resources. Very useful in daily status meetings for identifying newly broken subsystem features that could then be easily backed out or fixed.• Helped define and develop industry-standard test plan for client's initial FPGA implementation; collected requirements from designers/spec, prioritized with design team input.• Initial code coverage data collection and analysis, worked with designers to see if holes could/should be addressed.• First to prototype a simulation connecting all subsystems in simulator to exercise simple functionality, before feasible in lab.• Received client's “Thank You” award for verification of high-profile 5M gate ASIC.

Validation of the various processor models (SystemC/RTL/FPGA/Panève proprietary model) against each other, and against specified behavior, for a Big Data appliance under development. Grading of past tests and hardware (SystemC/verilog)/software testing approaches for inclusion in nightly regressions. Custom regression/automation/analysis utilities as needed. Specify new randomized test generation algorithms/targets for implementation. Management of automated clean compiler builds and light compiler/build debug. Leveraged worker that assists others in root-causing bugs of various sources, and tracing sources of error to design changes, software/compiler changes, tool/OS/platform changes, &c. Work with others to create metrics to assess quality and coverage. If practical, determine who is to blame for new bugs, with the assistance of various automated baselines, such that new errors can be corrected quickly while they are still cheap to fix. Manage, direct, and coordinate with others in related roles.

• Wrote and maintained self-checking C++/SystemC programs for constrained random verification of simulated hardware, maintained quality metrics and code coverage to ensure continuous quality of product.• Member of team that developed and maintained coverage metric computation and visualization package (Perl and SQL) for tracking hardware test quality. Co-developed and maintain data extraction and computation portion, awarded “SVL Star” award for 10x performance improvement to improve efficiency of massively parallel regressions, worked with team to specify a friendly web interface for coverage monitoring. Built and maintained regression utilities, specified, implemented, and documented new features.• Wrote reusable Perl/shell test generators, tools for managing patch trees, monitoring application performance on farm, mapping data.• Coursework: System C, SCV, System Verilog, 0-in Formal/CDC, Project Management Fundamentals

See CO Consulting for further details about this and other contracts

• Wrote AWK script to convert existing assertions to Sugar/PSL. Participated in PSL and System Verilog standardization process to ensure that common customer assertions were expressible.• Helped to drive roadmap for Sugar/PSL assertion-language support to cover critical early customer needs.• Wrote requirements for FormalCheck 3.1-3.5 as lead FormalCheck Product Engineer, incorporating rollout requirements from 10+ of the largest US & European semiconductor/electronics companies.• Led design/delivery of FormalCheck suite demonstrations at Design Automation Conference (DAC), 3 years.• Led development of training materials and labs for FormalCheck and effective assertion-writing techniques. • Worked with customers to understand need for common coverage between property checking/simulation.• Maintained technical, customer, and collateral continuity during 5 development/marketing transitions.

. Formal Verification and Simulation tool support/development for Bell Labs Design Automation (BLDA). Began work in AT&T Computer Systems Division (RIP), just post-divestiture, and started developing local tools for use in that org. Survived the Olivetti acquisition (RIP) and the NCR purchase/spinoff, and migrated into Bell Laboratories (SysCAD) to develop tools for use in all of AT&T hardware design. Helped (via development, and new roles in support, marketing, and sales) to migrate this into first an internally supported business, and then into one that gained increasing funding from outside companies, to become a self-sustaining business within the new Lucent. Eventually acquired by Cadence, with many good hopes for increased market share and growing profitability.

Simulation tool support/development for AT&T Computer Systems Division

See Lucent Technologies listing for further details

Research in Computer-Aided Geometric Design (CAGD) for Alpha-1 project