Corey Tsai Email & Phone Number

In charge of high-speed analog ASIC design team to develop Driver & TIA for Infinera products, starting from initial 10G NRZ system to latest 800G coherent optical systemDevelopment cycle consists • Front-end designo Spec definition/negotiation/documento Foundry selectiono Schematic design, simulation, layout o Design reviewso Top level chip integration and reticle assemblyo Tape-out verification: DRC, LVS• Back-end verification and testo ATE wafer screen test plan development, data review and debugo Coordinate initial wafer allocation and ensure die availability for all activitieso Chip bringup and RF characterization: BW, linearity (RF probing)o Work closely with optical module team to obtain optimal performance with proper ASIC settingso Design improvement/re-spin based on electrical and optical data• Production Supporto Technical support of any ATE issueso Optical module failure mode analysis of ASIC related issues