PLL Experience:• Designed and implemented a PLL reference clock receiver in 14nm Global Foundries process having an operating range of 100Mhz-800Mhz.• Designed and implemented a low noise 200Mhz PLL reference clock receiver in 14nm and 7nm finFET processes having a phase noise of -156dBc/Hz at 1Mhz• Performed functional verification and characterization of high-speed clock dividers, clock output buffers and level shifters• Designed and optimized low voltage bandgap in 14nm and 7nm finFET process capable of operation down to 1.08V supply across a temperature range of -40C-125C• Performed noise analysis and characterization of a pad cage containing a15Ghz VCO incorporating output loads, parasitic wire interconnect, pad and cables models to predict circuit performance prior to lab testing. • Assisted in the optimization of the PLL reference clock path from the crystal output to the receiver output by identifying and quantifying phase noise contributions from clock buffers, CPWs, clock muxes, and the reference clock receiver.Temperature Sensor Experience:• Characterized critical blocks including bandgap references, S/C integrator amplifier, and voltage comparators for use in a 10-bit temperature sensor • Successfully reduced power and operating voltage from 1.5V to 1.2V without compromising performance• Maintained and adhered to strict simulation plan to insure product performance

DDR I/O Experience:• Extensive knowledge of different standards: DDR3, DDR4, LPPDR3, LPPDR4, etc.• Experienced implementing solutions for different technologies and foundries including 28nm SOI, 16nm finFet and 14nm finFet.• Contributed to the profitable DDR I/O IP business by designing multi-standard high speed receivers with first silicon pass success.• Implemented novel ideas to improve performance issues including DCD related jitter and bias current variation with the use of on-chip calibration circuitry that has been proven successful in silicon through different customer system level tests.• Performed pre-layout design simulation and characterization as well as post layout verification, including post extraction, reliability verification, electrical overstress, EMIR and LTE (Local Thermal Effect) analysis.• Led the PD team in the floor planning and layout of the designs.

SERDES Design Experience: • Analog design experience includes op-amps, bias circuits, band gap references, temperature sensors, voltage regulators, resistor calibration circuits, Digital-to-Analog converters and crystal oscillators. Digital experience includes reclocking circuits, serializer and deserializer circuits with some exposure to driver design.• Performed transmit (TX) and receive (RX) eye compliance tests on 3.125Gbs and 6Gbs SerDes chips in a laboratory environment. Additional SerDes laboratory testing experience includes characterizing sinusoidal receive jitter based on IEEE 802.3 specification.• Designed and simulated receivers compliant to IEEE (802.3) 3.125Gbs specification, Infiniband 2.5Gbs, and PCI Express 2.5Gbs specifications.Services Projects:• Designed and simulated programmable low voltage detector circuits for power management IC.• Designed, simulated and laid out thermal diode temperature sensor.• Designed, simulated, floor planned and assisted in the layout of a 10-bit 2.4Mhz, 12-bit 600Khz and a 13-bit 3.3Mhz interpolating resistor ladder DACs.• Designed simulated and advised layout of single eFuse and eFuse 128 Efuse arrays using IBM's 130nm and 90nm CMOS processes.

Optimized the design of custom logic and pad buffers for HC11 and HC05microcontrollers.• Simulated custom logic on HC11 and HC05 microcontrollers using MCSCPICE.• Sized VDD and VSS pad rings for IR drop and electro migration.• Characterized gate coupled NMOS devices and SCR structures designed for ESD.• Gained valuable experience micro probing.