Key skills and experiences:• HDL & HVL: Verilog & System Verilog• Verification Methodologies: UVM, Assertion-based Verification• Programming languages: C & C++• Scripting Languages: Perl, TCL, Shell, MakeFile• Protocols: AMBA (AHB, APB & AXI), PCIe, JTAG, DDR, UART, SPI.• µP & µC: Zynq 7000, Atmega 328p, MSP430, ESP32, ESP8266• Creating and enhancing existing & new testcases in SV• Worked on complex RAM Memory IP, Constrained random TB• Functional verification fundamentals, Code coverage and Functional coverage• Constrained random testbenches• UVM RAL model & RAL coverage generation• Building verification environments using UVM methodology• Tools: - Wave: Vivado, ModelSim & SimVision - Verification: Questa, VCS, Verdi & Xcelium - Synthesis: Design Compiler - lint: VC Spyglass• Text editor: Vim, GVim, NP++Also got a good understanding of ASIC design flow, RTL to GDS design flow, and having a hands on experience in building System Verilog based testbench and UVM Verification testbenches for complex IP's