Cristobal Ramirez Email & Phone Number

Austin, Texas, United States

Austin, Texas, Estados Unidos

Core IP Design Team - VectorsWorking on micro-architecture and RTL design for the out-of-order high-performance SiFive's P470, P670, and P870 vector cores. Work responsibilities include:- Micro-architecture definition and RTL implementation- Early synthesis and timing analysis/fixes- RTL-level power analysis and reduction

Barcelona Y Alrededores, España

At BSC, I collaborated on two key RISC-V projects:European Processor Initiative (EPI) project.Working on performance evaluation, micro-architecture and RTL design for the high-performance RISC-V Vector Processing Unit (VPU) Vitruvius. Work responsibilities include:- Performance evaluation on the gem5 simulator for diferent configurations including: --- decoupled design --- number of physical vector registers --- vector length. Evaluating short(512-bit), medium(4096-bit) and very long vectors(16384-bit). --- in-order and out-of-order issue schemes. --- number of vector lanes (datapath width)- Micro-architecture definition and RTL implementation- Synthesis and timing analysis/fixesDesigning RISC-V-based Accelerators for next-generation Computers (DRAC) project.Working on micro-architecture and RTL design for the in-order and out-of-order high-performance superscalar Lagarto cores (based on RISC-V ISA). Work responsibilities include:- Micro-architecture definition and RTL implementation --- Lagarto Hun: In-order single issue 8-stages pipeline. ----- Design and implementation of the complete Lagarto Hun pipeline. --- Lagarto Ka: high-performance out-of-order superscalar pipeline ----- Branch predictors ----- out-of-order issue queues ----- integer functional units ----- FP fuctional units- Synthesis and timing analysis/fixes

Ciudad De México Y Alrededores, México

Working on micro-architecture and RTL design for the in-order and out-of-order high-performance superscalar Lagarto cores (based on MIPS ISA). Work responsibilities include:- Micro-architecture definition and RTL implementation --- Lagarto Hun: In-order single issue 8-stages pipeline. ----- Design and implementation of the complete Lagarto Hun pipeline. --- Lagarto Ka: high-performance out-of-order superscalar pipeline ----- Branch predictors ----- out-of-order issue queues ----- integer functional units ----- FP fuctional units

Phd, Computer Architecture

Activities and Societies: Computer Arquitecture For Parallel ParadigmsThesis: Adaptable register file organization for vector processors.

Education record

Activities and Societies: HiPEAC collaboration grant. School of Electrical and Computer Engineering. Deparment of Computer Science..

Master'S Degree In Innovation And Research In Informatics

Activities and Societies: Computer Architecture for parallel paradigmsThesis: Design and Implementation of an OoO Execution Engine.

Master'S Degree, Master Of Science In Computer Engineering

Activities and Societies: Microtechnology and Embedded Systems Lab Thesis: Design and Implementation of an OoO Execution Engine.

Bachelor'S Degree, Mechatronics Engineering