Provide FPGA-based customer solutions for accelerating flash-based storage in Datacenter applicaitons, leveraging Xilinx and ecosystem-partner NVMe IP.

Pre- and post-sales Xilinx FPGA support for top-tier customers.

Assembled a W-CDMA receiver prototyping FPGA platform, using MATLAB, Simulink, Xilinx System Generator and AccelDSP. Implemented DSP modules for an IIR Equalizer filter, de-spreader, re-spreader, and various other circuits. Worked with team on hardware/software design trade-off decisions. Setup hardware lab and specified test equipment purchases. Created customer demonstrations. Created and maintained company website.

Provided customer support, training, and consulting services for Celoxica's DK Handel-C FPGA compiler. Completed various consulting projects, including implementation of a Handel-C-based design for an image processing application, and verification of a verilog floating-point core, using verilog PLI. Created a demonstration showing FPGA acceleration of Mandelbrot set comp utations, using C, Handel -C and OpenGL.

HW Engineering Manager (7/04-1/06): Responsible for tactics, content review, project management and coordination, and people management for a 5-member FPGA Team. Participate in system architecture discussions. Provide technical assistance to FPGA team members as required. Ensure positive working relationship with and coordination between vendors, team, and internal customers. Identify and address developmental needs of the team’s members. Technical Team Leader (3/02-7/04): Responsible for FPGA development effort on ONS15600 and ONS15310 platforms. Wrote and reviewed design specifications. Provided technical guidance to the FPGA team members. Maintained detailed schedules. Wrote and simulated RTL code for a variety of SONET data interface, timing, data phase-aligner, and serial control applications.HW Engineer IV (2/00-3/02): Performed system-level tests on Stratum-3 timing core. Completed schematic entry of control card using Viewlogic.

Completed the design and debug of ATM datapath interface FPGA for SDSL modem. Converted FPGA into 30K-gate ASIC. Tasks included synthesis, static timing analysis, scan insertion, and test vector generation. Participated in ASIC lab validation. Completed sign-off of ASIC for production.

Technical Team Leader (10/97-8/99): Team Leader of FPGA designs for the MAXXIS ATM project. Responsible for 6 FPGA designs, including scheduling, technical guidance of four team members, and detailed design. Designs included UTOPIA1-to-UTOPIA2 interface, and UTOPA-to-switch fabric interface. Also contributed to system- and board-level architectures, and lab debugging of the prototype system. Technical Staff Member IV (10/95-10/97): Lead engineer on the design of a 150K-gate 0.4-micron CMOS digital ASIC for a SONET STS-1/DS3 interface for a broadband cross-connect. Responsible for the ASIC schedule, high-level architecture, simulation and verification test plan, and technical guidance of two engineers. Implemented and tested SONET Desynchronizer and Pointer Smoother Digital Filters on FPGA Breadboard. Technical Staff Member III (4/94-10/95): Designed SONET pointer processor and path overhead processor for a SONET STS-3/12 ASIC.Coordinated lab test effort of the ASIC.

Responsible for the integration of 90K gate digital CMOS ASIC into multi-board 68040-based VME bus system. Designed and synthesized 20K gates of 90K gate ASIC using VHDL and Synopsys. Wrote VHDL bus-functional models of MC68040 and support logic, and ran system-level VHDL simulations of above system.

AutoCAD drafting and scripting.