Pursue consulting work in the preparation of physical and electrical models for the design, modeling, simulation, and analysis of modern semiconductor device and interconnect technologies at the IC chip, IC package, and PC board levels.Current emphasis is on the pursuit of physical, electrical, and mechanical models for active semiconductor devices which correctly scale with lithographic dimensions from 180 nanometers down to 10 nanometers, as defined by the 2011 version of the International Technology Roadmap for Semiconductors (2011 ITRS).A major current emphasis is on the development and use of reliability physics-based CAD simulation tools to predict the impact of natural and artificial radiation sources on the production of Soft Error Rates (SER) and Soft Error Upsets (SEU) in semiconductor memories (DRAM, SRAM, and nonvolatile), in dynamic and static CMOS logic circuits, in Error Detection and Correction circuits (ECC) at the IC chip, IC package, and systems level, and in the individual functional blocks of ASIC and FPGA circuits at the IC chip level.