Dan Halperin
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Dan Halperin Email & Phone Number

Senior Solutions Manager and EMIR Tech Lead at Cadence Design Systems
Location: Greater Fort Collins Area, United States 15 work roles 3 schools
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Current company
Cadence Design Systems
Role
Senior Solutions Manager and EMIR Tech Lead
Location
Greater Fort Collins Area, United States
Company size
10387 employees

Who is Dan Halperin? Overview

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Dan Halperin is listed as Senior Solutions Manager and EMIR Tech Lead at Cadence Design Systems, a with 10387 employees, based in Greater Fort Collins Area, United States. AeroLeads shows a matched LinkedIn profile for Dan Halperin.

Dan Halperin previously worked as Senior Solutions Manager and EMIR Tech Lead at Cadence and Senior Principle Solutions Engineer and Tech Lead at Cadence Design Systems. Dan Halperin holds Phd, Electrical Engineering / Computer Engineering from University Of Illinois Urbana-Champaign.

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Cadence Design Systems

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Profile bio

About Dan Halperin

Highly experienced and successful electrical engineer with broad and deep background in IC electronics. Particular strengths in IC reliability, CAD tools, scripting, and design. Product and customer oriented. Demonstrated ability to deliver innovative solutions to hard problems.

Current workplace

Dan Halperin's current company

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Cadence Design Systems
Cadence Design Systems
Senior Solutions Manager and EMIR Tech Lead
Fort Collins, CO, US
Website
cadence.se
Employees
10387
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15 roles · 50 years

Dan Halperin work experience

A career timeline built from the work history available for this profile.

Senior Solutions Manager And Emir Tech Lead

Cadence

Fort Collins, Co, Us

Senior Cad Software Engineer

Intel Corporation

Santa Clara, California, Us

Part of a team that develops and supports parasitic extraction flows of analog and custom circuits. The flows are built around industry standard tools (Synopsys ICV and StarRC). Also supported an internal CAD latch reliability tool (metastability and soft error rate analysis). These flows are used by IC design teams across Intel.

Jan 2018 - Mar 2023

Technical Program Manager

Intel Corporation

Santa Clara, California, Us

Technical Program Manager for an initiative between Manufacturing Q&R and the CAD Team which was responsible for CAD tools that performed pre-silicon sign-off checks. Goal was to improve the alignment between Q&R requirements and the actual checks that the sign-off CAD tools performed.

Mar 2017 - Jan 2018

Engineering Manager For Reliability And Esd Flows

Intel Corporation

Santa Clara, California, Us

Lead a team of 8 Senior Software Engineers delivering sign-off CAD tools for RV (electromigration/self-heat/IR-drop) and ESD. These flows were built around industry standard tools (primarily Ansys Totem). These CAD tools were used by IC design teams across Intel and some external foundry customers.

Mar 2016 - Mar 2017

Senior Cad Software Engineer

Intel Corporation

Santa Clara, California, Us

Developed and supported CAD flow for RV analysis (electromigration/self-heat/IR-drop) built around industry standard tools (primarily Ansys Totem). This CAD flow was used by IC design teams across Intel and some external foundry customers.

Apr 2013 - Mar 2016

Senior Design Engineer

Intel Corporation

Santa Clara, California, Us

Technical Lead for the Interconnect RV Team for an Itanium and a Xeon microprocessor. Responsible for schedule, methodology, and requirements of the CAD tool flow for sign-off. Supported users, debugged issues, helped designers fix RV issues in their designs, and full chip roll-up of reliability metrics.

Jan 2005 - Apr 2013

Senior Design Engineer

Hewlett Packard (Hp)

Member of Interconnect RV Team for 3 Itanium microprocessors. Performed extensive testing of the CAD tool performing RV pre-silicon sign-off checks. Supported users of the tool and helped designers fix RV issues in their designs.

2001 - 2005 ~4 yrs

Technical Program Manager

Hewlett Packard (Hp)

Technical Program Manager for 2 PA-RISC designs. Worked with the Design Team and Fab to track schedules and manage risks to the program. Worked with Design Team, customers, and Fab to forecast needs of prototype wafers and parts and to manage inventory of prototypes.

1998 - 2001 ~3 yrs

Design Engineer

Hewlett Packard (Hp)

Member of the Design Team that delivered 15 PA-RISC microprocessors. Worked in the following areas: * Test strategy. On and off chip test hardware. Self-test hardware. * Chip power-on and debug * System performance tuning * Cache control algorithms and hardware implementation * Bus control hardware implementation * CAD tools for control logic hardware implementation * Logic verification * Customer support

1983 - 1998 ~15 yrs

Graduate Assistant

University Of Illinois Urbana-Champaign

Champaign, Il, Us

Teaching Assistant for digital electronics classes and labs.Research Assistant in the Coordinated Science Laboratory researching high reliability VLSI circuitry and signal processing algorithms and hardware.

1979 - 1983 ~4 yrs

Research Assistant

University Of Tennessee, Knoxville

Knoxville, Tn, Us

Developed image processing software and conducted image processing research in UT's Image Processing and Analysis Laboratory.

1978 - 1978
Team & coworkers

Colleagues at Cadence Design Systems

Other employees you can reach at cadence.se. View company contacts for 10387 employees →

SG Sanjay Gupta Sanjay Gupta Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India View → MY Madhuri Yellisetti Madhuri Yellisetti Colleague at Cadence Design SystemsBengaluru, Karnataka, India View → HY Huilin Ye Huilin Ye Colleague at Cadence Design SystemsAustin, Texas, United States View → VP Vijay Prakash M Vijay Prakash M Colleague at Cadence Design SystemsBengaluru, Karnataka, India View → MK Manimaran K Manimaran K Colleague at Cadence Design SystemsBengaluru, Karnataka, India View → FS Fengpeng Shi Fengpeng Shi Colleague at Cadence Design SystemsBeijing, China View → OS Ofer Steinberg Ofer Steinberg Colleague at Cadence Design SystemsNehora, South District, Israel View → AA Ashik Anuvar Ashik Anuvar Colleague at Cadence Design SystemsBengaluru, Karnataka, India View → LX Linfu Xiao Linfu Xiao Colleague at Cadence Design SystemsSan Jose, California, United States View → 刘 刘运花 刘运花 Colleague at Cadence Design SystemsChina View →
3 education records

Dan Halperin education

Phd, Electrical Engineering / Computer Engineering

University Of Illinois Urbana-Champaign

Msee, Electrical Enineering / Computer Engineering

University Of Illinois Urbana-Champaign

Bsee, Electrical Engineering

University Of Tennessee, Knoxville
FAQ

Frequently asked questions about Dan Halperin

Quick answers generated from the profile data available on this page.

What company does Dan Halperin work for?

Dan Halperin works for Cadence Design Systems.

What is Dan Halperin's role at Cadence Design Systems?

Dan Halperin is listed as Senior Solutions Manager and EMIR Tech Lead at Cadence Design Systems.

Where is Dan Halperin based?

Dan Halperin is based in Greater Fort Collins Area, United States while working with Cadence Design Systems.

What companies has Dan Halperin worked for?

Dan Halperin has worked for Cadence, Cadence Design Systems, Intel Corporation, Hewlett Packard (Hp), and University Of Illinois Urbana-Champaign.

Who are Dan Halperin's colleagues at Cadence Design Systems?

Dan Halperin's colleagues at Cadence Design Systems include Sanjay Gupta, Madhuri Yellisetti, Huilin Ye, Vijay Prakash M, and Manimaran K.

How can I contact Dan Halperin?

You can use AeroLeads to view verified contact signals for Dan Halperin at Cadence Design Systems, including work email, phone, and LinkedIn data when available.

What schools did Dan Halperin attend?

Dan Halperin holds Phd, Electrical Engineering / Computer Engineering from University Of Illinois Urbana-Champaign.

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