Dan Halperin Email and Phone Number

Part of a team that develops and supports parasitic extraction flows of analog and custom circuits. The flows are built around industry standard tools (Synopsys ICV and StarRC). Also supported an internal CAD latch reliability tool (metastability and soft error rate analysis). These flows are used by IC design teams across Intel.

Technical Program Manager for an initiative between Manufacturing Q&R and the CAD Team which was responsible for CAD tools that performed pre-silicon sign-off checks. Goal was to improve the alignment between Q&R requirements and the actual checks that the sign-off CAD tools performed.

Lead a team of 8 Senior Software Engineers delivering sign-off CAD tools for RV (electromigration/self-heat/IR-drop) and ESD. These flows were built around industry standard tools (primarily Ansys Totem). These CAD tools were used by IC design teams across Intel and some external foundry customers.

Developed and supported CAD flow for RV analysis (electromigration/self-heat/IR-drop) built around industry standard tools (primarily Ansys Totem). This CAD flow was used by IC design teams across Intel and some external foundry customers.

Technical Lead for the Interconnect RV Team for an Itanium and a Xeon microprocessor. Responsible for schedule, methodology, and requirements of the CAD tool flow for sign-off. Supported users, debugged issues, helped designers fix RV issues in their designs, and full chip roll-up of reliability metrics.

Member of Interconnect RV Team for 3 Itanium microprocessors. Performed extensive testing of the CAD tool performing RV pre-silicon sign-off checks. Supported users of the tool and helped designers fix RV issues in their designs.

Technical Program Manager for 2 PA-RISC designs. Worked with the Design Team and Fab to track schedules and manage risks to the program. Worked with Design Team, customers, and Fab to forecast needs of prototype wafers and parts and to manage inventory of prototypes.

Member of the Design Team that delivered 15 PA-RISC microprocessors. Worked in the following areas: * Test strategy. On and off chip test hardware. Self-test hardware. * Chip power-on and debug * System performance tuning * Cache control algorithms and hardware implementation * Bus control hardware implementation * CAD tools for control logic hardware implementation * Logic verification * Customer support

Teaching Assistant for digital electronics classes and labs.Research Assistant in the Coordinated Science Laboratory researching high reliability VLSI circuitry and signal processing algorithms and hardware.

Developed image processing software and conducted image processing research in UT's Image Processing and Analysis Laboratory.

Designed and debugged digital instrumentation. Developed CAD software.