Responsible for Trainium's (TRN1's) programmability strategy.Led full-stack integration of programmable cores into the TRN1, including requirement scoping, architecture, and software.Shipped PyTorch Custom Operator feature for TRN1's General-Purpose SIMD (GPSIMD) engine, allowing customers to program the TRN1 using the Torch C++ api. Featured in AWS re-invent keynote:

Founding engineer on AWS' first custom ML silicon server chip project, Inferentia (INF1).Developed SOC model from scratch for the INF1 and TRN1 SOC. The cycle-approximate pre-silicon model aided software development, power, and verification/validation teams.Inventions in computer architecture, quantization, compiler scheduling, and DV test generation (11 US patents)

Co-Instructor for Spring 2021 ELE-475/575 (senior/grad-level Computer Architecture) with Dr. Lisa Hsu of Microsoft. Incorporated industrial material and insights into the lectures.

Owned the cache-subsystems of the Hexagon DSP cycle-accurate model, including: I$/D$/L2$/TCM, cache coherence, prefetchers, compression engines, and AXI controller. Performed architectural exploration, RTL performance correlation, and workload analysis across 3 DSP generations.

A member of the Corona chip R&D team, led by Norm Jouppi, that designed a 3D many-core chip with a silicon-photonic interconnect. Invented optical token arbitration.The published work (Vantrease et al) is a a top-50 cited ISCA paper and recognized in the ISCA-50 retrospective series ( https://www.sigarch.org/what-are-the-most-cited-isca-papers/ https://sites.coecis.cornell.edu/isca50retrospective/ )