Daniel Correa Email & Phone Number

Cupertino, California, US

Eindhoven, Noord-Brabant, NL

• Digital Design Lead in Austin’s Mixed-Signal Automotive IP team
• Converted complex algorithm written in C, into SystemC, and then synthesized it to verilog RTL, using Cadence Tools.
• Responsible for the development and support of digital blocks such as Temp Sensor, DAC, Sinewave Generator, CORDIC algorithm, and part of the team that created a BIST solution for Sigma-Delta ADCs.
• Work closely with system engineers and architects to implement next-generation IPs

Eindhoven, Noord-Brabant, NL

• Implemeted complex low power architecture for ARM multi-core-multi-voltage ULP MCU design on 28FDSOI technology using CPF. This specific project had over 40 different power-domain and over 20 power-modes. First MCU.
• Responsible for entire RTL-GDS backend flow for NVM digital controller/wrapper. Including synthesis, scan insertion, floorplaning, P&R, CTS, STA analysis and signoff;
• Worked on a script that placed triple voting flops with a minimum distance from each other on EDI to meet SER/ISO2662/FMEA safety requirements;
• Co-createad a program pulse algorithm that reduced the NVM program time up to 40% by analyzing the program data prior to writing to the flash;
• Created a new flow to detect hard to find cross domain clock violations on a mixed-signal design. This flow could detect CDC violations during simulation run-time;
• Implemeted several ECOs for multiple projects, including manual ECOS, metal-only ECOs and Conformal-LEC generated ECOs

San Jose, CA, US