Hardware Design Engineer
CurrentWork as hardware designer (Cadence workflow using schematic entry and Verilog RTL compiler). Implemented ultra low power circuit design for hearing applications. Worked on various hardware blocks. The largest being a reworked wireless system (mainly channel coding and DMA control to processor memory). Included simulation, testbench and firmware verification. Experience with ultra low power design, including clock gating, various clock domains etc. Also experience with power simulation using toggle files in Cadence workflow.Worked on future concepts, including Tensilica LX4, ARM M0, RTOS, AMBA AHB/APB and System C. Work on prototypes using these technologies.Also partial work in system engineering group as consultant.