Daniel Beckmeier Email & Phone Number

San Francisco, California, United States

San Francisco, California, Us

• Facilitate DFMEA and develop DfR design rules during the early chip design phase.• Develop silicon chip package level and board level testing plans to assess and validate Cruise in-house silicon chips and third-party chips for Cruise AV applications.• For validation tests at Cruise lab and local facilities, own test preparation, authorize test standard operating procedures (SOP), design test setup, and work with technicians to execute/oversee test executions.• For validation tests at vendors, work with vendor reliability engineers to develop proper test plans, review/audit supplier test setup, and drive supplier execution.• Analyze test data and collaborate with cross-functional teams on failure root cause analysis and develop proper mitigations. • Collaborate with other Cruise reliability engineers on compute level and other module level testing.• Participate in design reviews to ensure past lessons learned and best practices are incorporated.• Participate or lead DFMEA through the entire product development cycle for chip failure modes and effect identifications, detections, and preventions.

Santa Clara, California, Us

• Characterizing CMOS device and interconnect FEOL and BEOL reliability.• Working in conjunction with process integration and technology developmentengineers to provide reliability feedback during technology development. • Supporting intrinsic device and interconnect level qualification.• Working closely with Design Engineering to enhance aging models for key analog anddigital circuits, develop methods for validating analog and digital circuit degradation,SOA checking to enhance built-in reliability.• Developing new acceleration techniques, test methods and analytical tools to providefast and effective feedback for process, product, and test optimization on reliabilityissues• Determining reliability requirements and technology targets of components toachieve company, customer, and other reliability objectives.• Influencing design, process, product, test, and/or system solutions to enable aggressive scaling of Intel's NVM technologies• Working in cross-functional and cross-company groups of engineers on multi-disciplinary technical projects to solve complex reliability issuesduring technology development and ramp to high-volume manufacturing.• Working with reliability lab technicians for data collection and analysis.

Scottsdale, Arizona, Us

• Reliability characterization of Front End of Line (FEOL) devices, BEOL, and materials• Working with process and technology development teams to assess FEOL reliability of new semiconductor processes• Reliability swim lane owner for an advanced BCD (Bipolar,CMOS,DMOS) technology• Ownership of PID test structures, test plans, analysis, and design rules• Design and implementation of test structures for reliability characterization, including layout in Cadence environment• Designing, building, and maintaining test systems for reliability measurements• Developing robust and efficient data analysis flows for raw data and report generation, archiving, and recall• Working on PID and fWLR standards in JEDEC task groups

Neubiberg, München, De

• Fast Wafer Level Reliability Monitoring implementations in semiconductor fabs and foundries• Interface for technology reliability monitoring for foundries and one internal fab• Plasma Induced Damage (PID) technology reliability qualifications• Methodology development for PID monitoring• Antenna design rule definition for semiconductor products to prevent charging damage during production• Training of internal and external experts on CMOS reliability• Lead of internal teams for technology qualification

Neubiberg, München, De

• Technology reliability qualifications for plasma process induced damage (PID)• Implementation of wafer-level reliability monitoring in fabs and foundries• Methodology development for reliability monitoring and PID

Neubiberg, Bavaria, De

• Development of a semiconductor memory based on fullerenes (planning, processing and electrical characterization)• Analytics (STM, AFM, REM, FTIR)• Holding student tutorials and practicals• Supervision of diploma students

Dr.-Ing., Electrical Engineering / Semiconductors

Diploma, Physics

Semester Abroad (Erasmus Stipend), Physics