Daniel Duggan Email & Phone Number

Brookfield, CT, US

- Overall responsibility for Semiconductor Reticle production site; 119 employees- P&L accountability with expectations to deliver annual operating plan- Driver of operational KPI improvements; OEE, Yield & service- Leading a safe and injury free working environment- Commercial cooperation for growth; new business

Brookfield, CT, US

- Overall responsibility for Semiconductor Reticle production site; 75 employees- P&L accountability with expectations to deliver annual operating plan- Driver of operational KPI improvements; OEE, Yield & service- Leading a safe and injury free working environment- Commercial cooperation for growth; new business

Newport, Wales, GB

Zurich, -, CH

• 200mm and 300mm wafer reclaimResponsibilities:-
• Manager of process engineer department, responsible for graduate process engineers and four shift techs. Responsible for the hiring, staff restructuring and staff career development through mentoring.
• Member of the senior management team in Pure Wafer.
• Responsible for the factory process and mechanical yield.
• Customer presentations along with technical innovation projects presented to global accounts.
• Cost reduction – reducing monthly consumable costs from £341,000 to £191,000 in six months.

Neubiberg, München, DE

• Apr 2006 – Aug 2007 Snr Shift Support Process Engineer – IRN LtdDue to a poor performing night shift I was asked to mentor all manufacturing staff on shift:
• Managing R+M engineers, Process Technicians, operators on shift priorities.
• Responsible for all process and manufacturing decisions (all area’s of the fab covered, Photo, Etch, Diffusion, films, implant, defectivity) and scrap reduction actions on shift (using 8D methodology).
• Driving process improvements on shift.July 2004 – Apr 2006 Snr Process Engineer – IRN LtdResponsible for the processes run on various wet etch/cleans and CVD deposition machines:
• Primary role has been the purchasing / commissioning and qualification to manufacturing of new tools to support current fab ramp, This involved project management of various departments from the facilities hook up.
• Implementing operating procedures including training of operators and technical staff on the machine operations.

Santa Clara, California, US

• Responsibilities:-
• Low-k PECVD Process owner for Fab24 startup. (0.65um 300mm)
• Assignment in US Intel in D1C ‘Intel’s leading edge development fab ensuring that the low-k process was robust for manufacturing transfer. During assignment was key member of process taskforce, which ended in redesign.
• Fab24 low-k Statistical Process Control team leader. Responsible for the Cpk improvement actions and driving continuous improvement within the module.

• Projects:1)Process development on new ORION™ Ultra low-k PECVD film (k 2.2 to 1.9) both 200mm and 300mm wafers.2)Process startup of new 300mm CVD tool: 300mm Planar fxP:
• low-k dielectric deposition (using methyl-silane and hydrogen peroxide)
• ‘lower’ k etch stops (alternatives to SiN i.e. Silicon Carbide)3)Optoelectronic development: Team leader in optoelectronic development process.
• Plasma deposition of silicon oxide films with very tight RI specification. 4)Processing numerous customer samples using one or more of Trikon’s CVD process applications.