Daniel Koontz Email & Phone Number

Chapel Hill, Nc, Us

Redmond, Washington, Us

San Diego, Ca, Us

• Performing physical verification in Calibre for all Snapdragon CPU designs in 28nm, 14nm, 10nm and 7nm• Floorplanning complex L2 cache macros which typically include unique layouts to accommodate large data arrays, analog power management macros, multiple CPU cores, preplaced data path logic, and 10k+ I/O pins• Performing place and route in ICC2 on L2 cache macros to analyze early timing and routing congestion• Consulting with logic designers for possible architectural changes when timing or routing issues are found• Working closely with synthesis team to group logic to improve timing and routability• Performing ECOs in ICC2 to fix logic defects and applying Primetime DMSA ECOs to close timing at 3 GHz• Contributing to a suite of design methodology scripts for custom CPU core design

Clifton, New Jersey, Us

· Project management of lighting system installations· Assisting in the design and integration of lighting systems for all types of entertainment · Producing power and control riser diagrams for lighting systems using AutoCAD· Producing lighting system drawings showing electrical distribution and support structures

Munich, ., De

· Created and modified full custom analog and digital physical design for DRAM chips· Verified 70nm DRAM layout for LVS and DRC compliance with proprietary design rules· Investigated top down floorplanning methodologies to improve time to market and significantly reduce die size

San Diego, Ca, Us

· Performed place and route in Astro with timing closure using Star-RC and Primetime· Verified 90 nm physical designs for DRC/LVS in Hercules and Calibre· Performed floorplanning, power grid design and analysis of design blocks using First Encounter· Documented design results and methodology in a shared wiki environment· Developed various scripts in Scheme and Perl to facilitate the design process

Wilmington, Ma, Us

· Performed place and route on a large synthesized processor core with a extremely challenging floorplan· Conferred with timing analysis engineer to close timing in Apollo using Star-RC and Primetime· Verified finished designs for DRC/LVS using Hercules

· Developed a back-end (gate-level netlist to verified GDSII) flow from the ground up · Evaluated and recommended CAD tools for purchase · Supported local CAD tools including tool installation and license administration · Utilized Magma tools for block level and full chip place and route · Performed signal integrity and power rail analysis with Simplex tools · Verified finished layout for design rule errors using Hercules and Calibre Integrated Circuit

Us

· Utilized Apollo for block level and full chip place and route · Acted as lead for the physical design of a full chip network processor · Performed timing closure of block level standard cell designs · Completed layout and verification of high speed mixed signal designs · Supported local CAD tools including tool installation and license administration · Interfaced with EDA tool vendors and fellow CAD Engineers across all PMC-Sierra sites · Provided and/or facilitated tool and design flow training for the Allentown site · Led a company-wide task group investigating mixed signal system modeling methodologies

Murray Hill, Nj, Us

· Designed and simulated transistor level circuits · Coordinated physical design of circuits · Generated functional vectors to verify circuit timing · Participated in continual peer review of circuit designs · Verified the circuits and functional models included in a chip design · Contributed to product design documentation

Murray Hill, Nj, Us

· Introduced Design Planner and IC Craftsman into the full chip place and route flow · Pioneered use of hierarchical LVS and DRC verification tools on a quad core modem system on a chip (SOC) · Utilized Apollo for block level and full chip place and route · Acted as lead for the physical design of three full chips that included extensive custom routing · Guided blocks and full chips through the entire back-end verification process · Prepared and submitted full chip layouts to mask