Daniel Lepkowski Email & Phone Number

Singapore

Lead efforts towards commercialization of a hybrid CMOS+III-V integrated circuits platform. This includes: Serving as technical point of contact for fab relationshipsIdentifying target commercial areasDeveloping product and technology roadmapDesign of novel ICs Directing Test/FA efforts

Singapore

One of the first 5 employees hired into this startup focusing on creating integrated III-V + CMOS optoelectronic systems. This is an evolution of my prior role at SMART with an effort towards commercialization.My role, while primarily focused on hybrid circuit design of novel integrated SOCs. it also, includes leading Probe/test development efforts, driving yield improvement efforts with partner foundries, and directing failure analysis efforts.nscinnovation.com

Focused on novel circuit design architectures and design considerations for integration of III-V semiconductor devices integrated directly on the ubiquitous Si CMOS platform. These integrated hybrid III-V/Si circuits have the potential to add new functionality to existing Si ICs in the upcoming Post Moore's Law era.

Columbus, Ohio

National Science Foundation Graduate Research Fellow pursuing a PhD in Electrical Engineering with a focus on semiconductor materials and devices. Perform research on optimization of growth and behavior of multi junction solar cells for terrestrial and space applications. Current research focus is on design and growth of of III-V/Si tandem solar cells.

Dallas, Texas

2nd summer as a failure analysis engineering intern. This summer I worked in the HVAL group supporting mostly the mixed signal automotive product lines. My primary project was designing and implementing a set up for cold temperature laser based isolation techniques as well as supporting the customer returns that required these techniques. On top of this I promoted utilization of backside FA techniques for analog devices as well as the adoption of advanced test techniques for isolating failures in digital cores of mixed signal devices.Lastly I performed Analog circuit analysis as well as FIB cuts and pads to determine the physical failure mechanisms in analog devices.

Baton Rouge, Louisiana Area

Operate many types of laboratory equipment as well as to characterize and manufacture alloys for magneto caloric effect studies. The characterization includes: structural studies with an X-ray Diffractometer, Magnetization measurements using a Quantum designs SQUID Magnetometer. This position also allows me to operate the Pulsed Laser Deposition system for creating magnetic or superconducting thin films. These films can then be studied by the above methods as well as Magneto-optic kerr effect.

Dallas/Fort Worth Area

This internship was 2 fold. First was learning to be a failure analysis engineer in the automotive microcontroller group. I supported both electrical failure analysis activities as well as physical failure analysis. Secondly my project also consisted of enhancing the labs Electrical Failure Isolation capabilities on digital blocks in analog technology nodes with heavily doped buried regions (NBL). Specifically Laser voltage probing and laser voltage imaging, two techniques utilized typically in the digital FA flow to debug complex issues with timing and device operation.Tool Use includes:FIBSEM Scanning acoustic microscopeX-ray fluorescencePhoton emission microscope DCG Systems Meridian Polishing wheelsHigh mag optical scopesHigh concentration acid and solvent work

Gaithersburg, Md

Performed research on magneto caloric materials, while learning how to operate in a laboratory environment. I fabricated alloys, characterized their metolographic, magnetic and structural properties using a variety of laboratory technology. These include: Scanning Electron Microscope, SQUID Magnetometer, and Electron Backscatter Diffraction. During this experience I broadened my knowledge of materials science and magnetism through the literature review as well as hands on experimental work.

My responsibilities included designing and completing a graduate level research project that is currently in the process of being published. This included fabricating semiconducting thin films using Atomic Layer Deposition and characterizing these films by a variety of methods. These methods included: 4 probe resistivity, Atomic force microscopy, UV/Vis spectrometry, Elipsometry, and X-ray diffractometry

Doctor Of Philosophy (Phd), Electrical Engineering

Bachelor Of Science (Bs), Electrical And Electronics Engineering

3.99 GPA LSU Academic Scholars Award LSU Chancellor's Honor Roll (7 semesters) Baker Hughes EE Scholarship American Association of Sugar.