Daniel M. Email & Phone Number

2002-2006Programable Logic Development: Actel FPGAs, Alterra PLDs and FPGAs, and Xilinx FPGAs. Designed/implemented south bridge FPGA for PowerPC processor boards.Implemented in VHDL along with associated test benches:•Control Register set•I2C Interface (master and slave)•SPI Interface (master and slave)•IDE interface (Master)•LPC Interface (Slave)2005-2010 Quality Management (ISO 9001)Assisted in ISO 9001 Quality Management System Implementations and in passing the Initial audit, as well as annual external audits. Wrote and implemented procedures for:Electrostatic Discharge (ESD) Control based on the guidance of ANSI / ESDA 20.20Calibrated equipment procurement, tracking, use, and maintenance based on ISO 10012 and ISO 17025Company processesPerformed process auditsOpened, Investigated, Implemented Corrective and Preventative Actions (CARs and PARs) Assisted in selecting and tracking process metrics 2007-CurrentProject/Program/Design ManagerBoard level design of CompactPCI (CPCI) and VPV backplanes, PCIe edge cards, VME boards, PMC, XMC, and VPX modules. PowerPC processor boards, Conduction and Forced-air chassis for ground, vehicle, and airborne use.Program Manager/Chief Architect/Design Manager for multiple avionics chassis programs.Prime contractor point of contactManaged design teams (of electrical mechanical engineers primarily)Managed project scheduleConducted design reviews (kickoff, preliminary design review, critical design review, test readiness review, productions readiness reviews - with primes and government officials)Electromagnetic Interference (EMI) / Electromagnetic Compatibility (EMI)Design to meet and compliance testing against MIL-STD-461 and DO-160Environmental Requirements Design to meet and compliance testing against MIL-STD-810 and DO-160Power BusDesign to meet MIL-STD-704 and compliance testing against MIL-HDBK-704-8

Madison, Wisconsin.

Designed / implemented telecomunication board logic as well as south bridges for PowerPC processor boards with Cypress PLDs, as well as Altera PLDs and FPGAs.Implement in VHDL along with associated test benches:•PCI Target Interface•DRAM controller•Control Register set•I2C Interface (master and slave)•SPI Interface (master and slave)•NOR Flash Interface•etc.