High Speed IO Architecture Lead the integration at SOC level of different Phys from external and internal providers including protocols like USB, PCIe and UCIe among others for Client segment. This includes benchmarking IPs from different vendors, driving the definition of Phy electrical requirements and SOC floor planning, alongside the coordination among different stake holders for SOC integration and validation, package integration, and platform interaction. Additionally, provided extensive support for post-silicon validation including debug efforts, experiment design, results review and collaborated with firmware development.Analog circuits design Developed a novel model for High Volume Manufacturing testing thru a simplified-dedicated IO interface reducing test time, driving significant costs savings for intel client products. Lead and coordinated the development of several analog IPs used in Intel clients segment including Voltage regulators, oscillators, Voltage Supply Monitors and circuits tailored for Intel’s client products, from conception to post-silicon validation. Benchmarked different advanced CMOS Fabrication nodes and evaluated performance of critical Circuits, helping the organization to decide on process technologies for future projects and influencing the development of Intel’s future fabrication nodes. SOC Full chip clock design and integration lead Led and coordinated the design efforts for full-chip clock distribution for some of Intel’s 10nm client and Graphics products, including the design and integration of propagated clocks and spine design for clocks in the range of 100MHz to 8GHz. Participated in SOC level floor planning workgroups to optimize die size and clock performance.

Display clocking solutions owner Owned the back-end implementation of the clock distribution solution for the display subsystem in Intel’s 10nm client products taking the design to Tape-In, thru a rigorous design flow that included custom circuit design for high speed designs, APR of low speed blocks, formal verification, timing modeling and analysis, analog simulations, reliability and noise analysis. Designed a custom solution for propagated clocks distribution for high-speed, low jitter, low power, and low duty cycle distortion in the range of 4GHz to 8GHz. Influenced floor planning of the display subsystem for quick and efficient timing convergence. Ownership and responsibilities extended into Si Debug and characterization support.Digital PLL designConducted introductory studies for digital PLLs architectures. Owned the design of several building blocks of a digital PLL for Intel’s 10nm client Products and test chips, including frequency dividers, Digitally-Controlled Oscillators, duty-cycle adjusters and several observability and test-oriented blocks for low-power and high-performance operation.Completed functional verification thru static and dynamic simulations, guided layout implementation, and reviewed performance, reliability and aging results. Analog PLL design Owned the design of several analog building blocks of analog PLL as charge pumps, and low-pass filters. Conducted analog-style simulations, to verify functionality, stability, performance, and reliability analysis. Fine tune designs as needed per fabrication process adjustments for 22nm and 14nm fabrication node.Voltage Regulators Collaborated in the design and verification of several different voltage regulators architectures for several of Intel’s 14nm products, stablished test benches for functional simulations, stability analysis, load and line regulation characterization.

Clock electrical integrity checksGenerated PERL/TCL scripts for clock data mining analysis to identify potential risky electrical integrity issues in the clock path.Verified robustness of power connection to dedicated clock cells along the entire SOC, to guarantee quality of the clocks in the SOC. Voltage RegulatorsOwned the characterization and fine tuning of a linear voltage regulator for low power scenarios, including functional simulations, stability analysis, and performance, load and line regulation, as well as reliability and aging simulations for Intel’s 22nm lead vehicle product.DFT and observability block characterizationCharacterized all DFT blocks for several different IPs (thermal sensors, PLLs, Voltage regulators…) to guarantee silicon observability and debug ability.

Conducted industry sponsored research in the front-end circuitry of ultrasound transmitters; analyzed the methods currently used and studied the feasibility of implementing a completely analog ultrasound transmitter to improve the quality of medical imaging.

Worked in conjunction with faculty to stablish a weekly lab session for undergraduate students covering the fundamentals on semiconductor devices and circuits, and linear circuits. Designed, tested and validated the experiments, and wrote the guidelines for students to follow in the laboratory. Worked with Department laboratory staff to procure the right components and devices needed to conduct the experiments.Provided basic training in electronics lab equipment operation (Voltmeter, osciloscopes, power supplies, signal generators...)

Planned, developed and conducted letures for an Undergraduate Course in Non-linear electronic Circuits, covering multivibrators, positive feedback applications, basics on ADCs and DACs, Phase Locked Loops, and switch mode power supplies.

Addressed a weekly lab or lecture session on Different Electrical Engineering topics as a support for Undergraduate students, some of the topics covered were: Analog Communication System, LogicCircuit Design, Processor’s Architecture, Linear and non-linear electronic circuits