Daniel Mcgrath Email & Phone Number

United States

Ottawa, ON, CA

Research & Mentoring

Image sensor device physics, design and technology: small pixel, global shutter, ToF and III-V GMAPD, process integration, yield improvement. Special expertise in dark current and defects.

Shenzhen, Guangdong, CN

London, GB

San Jose, California, US

Pixel Device Physics with emphasis on dark current & hot pixels; program leadership for dark current & hot pixel reduction for DSLR image sensor.

San Jose, California, US

US

Independent consultant on image sensors, technology transfer to external foundries and technology management.

• Program management: 5 Mpix CMOS image sensor product; joint differentiated technology development with external foundry leading to 1.4m pixel; developing design flow & controlling tapeout of multiproject mask sets.
• Pixel design for pinned photodiode pixel in 0.18 m & 0.11m CMOS technology including dark current, bright point defects, dynamic range & responsivity

• Pixel design and associated analog technology for a start-up based on CMOS imaging technology
• Debugged production test of sensons at Taiwan vendor

• Responsible for developing image sensor technology, including CMOS image sensor arrays for system-on-a-chip products; close coordination with manufacturing, development and business operations in France and U. S.
• Program manager with responsibility as contact to key customer; interface to mixed-signal ASIC design team & product engineering; work with Cadence layout and integration tools to support two imaging SOC designs.
• Development of imaging technology within SOC flow for 0.25m and 0.18m process technologies. Device and circuit design using SPICE, Silvaco and Mathematica.

• Manager of group designing image acquisition systems based on CMOS active pixel technology integrated with synthesized digital cores & application specific analog cores. Participated in specification & design.
• Architecture and design of series of CMOS imaging chips as technology demonstrators in 1.6m to 0.5m process technology culminating in (a) SOC with 600,000 pixel array, 10-bit a-to-d, on-board timing, and.
• Managed four engineers involved in circuit design, digital design, FPGA-based PC-board systems, embedded microcontroller programming and device characterization. Worked directly with HSPICE, Mentor, Model Technology.
• Experience in program management including specification, budgeting and planning. Use of MS Project.
• Individual contributor with group researching novel approaches to electronic image acquisition. Technical responsibility to develop new directions for imaging products.
• Device physicist & designer of CCD image sensors for photographic imagery

Dallas, TX, US

• Device physics, process research and design related to CCD image sensors for military, scientific & commercial applications; first design & fabrication of a one million pixel CCD imager

Ph.D., Physics

B.S. In Honors, Physics