Daniel Su Email and Phone Number

ꞏ Led the transfer of a GaN FET emulated bootstrap IP to a new process, ensuring compatibility with isolated tank/well, physical layout requirements, timing, operation, and overall functionalityꞏ Identified overdesigned circuit schematics, redesigning to achieve a 10% area reduction of the overall circuitꞏ Performed risk management from fabrication process differences and reviewed tradeoffs between component performance and cost, resulting in component specification re-evaluation due to component max ratingsꞏ Implemented several RTL testbench IP for performance coverage through maestro to pipeline performance and regression analysis including gate level parasitic effectsꞏ Designed for a current limiting circuit in Cadence, initially achieving 50% accuracy due to fabrication differences and improved accuracy to 20% through PVT optimization for an older technology process

ꞏ Developed, maintained, and debugged UVM-based testbenches and test plans to verify power management circuit designs through performance analysis through Simvision and coverage metricsꞏ Developed scripts between Python and Verilog AMS to pipeline test generation reducing manual intervention and ensuring continuous verification including failure assertions ꞏ Scripted a real number model using EE components in System Verilog for the LDO power management system accounting for startup time, overshoot, attenuation, noise, and settling timeꞏ Created an innovative design tool allowing for Spectre simulation values to be used in a System Verilog block, significantly improving device process transfers and reducing analog simulation time

ꞏ Reviewed product process flows and collaborated with fabrication sites and managers to identify opportunities for workflow optimization, aiming to reduce time to marketꞏ Conducted SOS analytics and performed a deep dive on yield failures during testing, pinpointing the root causes to enhace product reliability and performanceꞏ Executed a deep analysis of potential false failures and extracted data from a failed wafer skeleton, ultimately demonstrating the validity of these false failures and acheiving around $100k in annual savings.

ꞏ Analyzed, planned, executed, maintained, and improved the production processes for several high running devices; methodically documented findings and explanations ꞏ Staged production improvements for 4 different devices with the estimated savings of over $150kꞏ Grasped a deep understanding of 3 different software interfaces in a short amount of time; documented procedures to smooth out the project transferring process at the end of the internshipꞏ Took initiative to work with test, fabrication, and design engineers to discuss test/limit improvementsꞏ Proposed an innovative idea to further increase the efficiency of the statistical outlier program ꞏ Created and presented all 4 projects and results with recommendations at the end of the internship

ꞏ Optimized and reconfigure old machine learning code that uses genetic algorithm in MatLab to authenticate experimental data of a biosensor currently used for COVID detection ꞏ Created a random material generator algorithm that accounts for the probability density of the carbon nanotube and graphene compositions by using reference magnified photo capturesꞏ Designed the interface in MatLab to be easily reconfigured to vary the probability density function, material layout, etc.

ꞏ Backend development of a website in C# that was used to limit the spread of COVID by taking in student input to help colleges prioritize safety features implemented in halls, gyms, and public areas

ꞏ Observed and learned about projects on hotels, architecture, airports, and military basesꞏ Reviewed documentation on Guam military base electrical systems with limited information on transformers, backup generators, and structural electrical circuitry