Physical Design Lead
Current
Nov 2023 - Present
AeroLeads people directory · profile
Daniel Talmon Email & Phone Number
Principal Engineer Physical Design
at
Rain AI
1 work email found
@gigoptix.com
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Engineer Physical Design
Location
San Francisco Bay Area, United States, United States
Who is Daniel Talmon? Overview
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Quick answer
Daniel Talmon is listed as Principal Engineer Physical Design at Rain AI, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at gigoptix.com and a matched LinkedIn profile for Daniel Talmon.
Daniel Talmon previously worked as Physical Design Lead at Rain Ai and Physical Design Lead at Aeva. Daniel Talmon holds Bachelor Of Applied Science - Basc, Electrical, Electronics And Communications Engineering from Technion - Israel Institute Of Technology.
Company email context
Email format at Rain AI
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{first_initial}{last}@gigoptix.com
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AeroLeads found 1 current-domain work email signal for Daniel Talmon. Compare company email patterns before reaching out.
Profile bio
About Daniel Talmon
15+ years experience in Physical design and ASIC Design flowsTechnical lead and individual contributor. Vendors and project management for ASIC and SOC designs.Owns Physical implementation and Methodology flows, Synthesis and Integration flows, RTL / netlist to GDS, using advanced nodes down to 7nm. Key contributor to first pass tapeout silicon success, PPA, QOR and chip cost reduction.Responsible for IP selection, evaluation and integration. Foundry, CAD and EDA vendors contact.Chip Design focal point, working and coordinating with Architecture, Frontend, Design verification, Analog design and Operations . Experienced in all Full chip and Block, Partition design cycles: SDC, floorplan, placement, clock tree synthesis, route, STA, Formal, Physical verification, timing closure and power optimization, Logical and physical ECO flows ( pre and post mask, FIB )Solid knowledge in Libraries and design abstractions, hierarchical and full chip implementation flows, STA,Digital circuit design, RTL Verilog, CTS, DV, PV, Architecture, DFT, Signal integrity, etc ...Experience with EDA tools from: Cadence, Synopsys, Mentor, …Innovus, ICC, DC, DCT, PrimeTime, Tempus, ...
Listed skills include Static Timing Analysis, Asic, Vlsi, Physical Design, and 15 others.
Current workplace
Daniel Talmon's current company
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10 roles · 26 years
Daniel Talmon work experience
A career timeline built from the work history available for this profile.
Physical Design Lead
Nov 2022 - Nov 2023
Principal Engineer Physical Design
Apr 2021 - Nov 2022
Sr. Principal Physical Design Engineer
Jan 2020 - Apr 2021
Principal Physical Design Engineer
Lead and manage all Chip Physical design, Synthesis and Methodology activities. Drive design PPA and QOR. Own production RTL to tapeout complete cycle responsibilities, support silicon bringup.Vendor management, IP performance evaluation, development and integration. EDA, CAD, Foundry and IP vendors contact.
2017 - 2020
~3 yrs
Sr. Staff Physical Design Engineer
Supporting strategic tier one customer (High performance CPU), flow migration and tool integration. Daily support for test chips, Hier flows and implementation. Actively working with R&D on new EDA features development, driving PPA and QOR improvements. EDA Users mentoring and problem solving (Also for SOCs, Mixed Signal and Libarary groups).
2015 - 2017
~2 yrs
Sr. Physical Design Engineer
Physical design, Integration flow ownership, Full chip implementation, Partition implementation, Test chip, vendor management
2012 - 2015
~3 yrs
Sr. Physical / Cad Engineer
Chipx (Acquired By Gigoptix)
Library characterization, Physical design, Structured Asic and SOC full chip tapeouts.EDA and CAD flows development, from XCELL unit to std cell to complete PDK
2006 - 2012
~6 yrs
Asic / Vlsi Physical Design Engineer
DSP cores physical design implementation,STA, Modeling flow for complex cells in semi custom designs
2004 - 2006
~2 yrs
Asic / Vlsi Engineer
Library characterization, STA full chip, core and block (gatelevel and transistor level) Digital circuit design, Semi custom design flow
2000 - 2004
~4 yrs
1 education record
Daniel Talmon education
-
Technion - Israel Institute Of Technology
FAQ
Frequently asked questions about Daniel Talmon
Quick answers generated from the profile data available on this page.
What company does Daniel Talmon work for?
Daniel Talmon works for Rain AI.
What is Daniel Talmon's role at Rain AI?
Daniel Talmon is listed as Principal Engineer Physical Design at Rain AI.
What is Daniel Talmon's email address?
AeroLeads has found 1 work email signal at @gigoptix.com for Daniel Talmon at Rain AI.
Where is Daniel Talmon based?
Daniel Talmon is based in San Francisco Bay Area, United States, United States while working with Rain AI.
What companies has Daniel Talmon worked for?
Daniel Talmon has worked for Rain Ai, Aeva, Lightmatter, Innovium Inc., and Knowles Intelligent Audio.
How can I contact Daniel Talmon?
You can use AeroLeads to view verified contact signals for Daniel Talmon at Rain AI, including work email, phone, and LinkedIn data when available.
What schools did Daniel Talmon attend?
Daniel Talmon holds Bachelor Of Applied Science - Basc, Electrical, Electronics And Communications Engineering from Technion - Israel Institute Of Technology.
What skills is Daniel Talmon known for?
Daniel Talmon is listed with skills including Static Timing Analysis, Asic, Vlsi, Physical Design, Eda, Soc, Tcl, and Perl.
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