Daniel Toet Email & Phone Number

Fremont, California, United States

Silicon Valley, California, United States

• Defined specification of OLED printing system and its subsystems, incl. in-depth error budget analysis• Proposed concepts for/led fabrication of various test and calibration stations (incl. flight control/alignment)• Leading efforts to characterize and improve line uniformity, resulting in successful customer demonstration• Leading various development programs, incl. print die packaging and inspection/metrology of printed lines.• Coordinating OLED printing process development activities • Generated system use case and test plan documents

Fremont, California

Leading a team of HW engineers and consultants in the design, integration and manufacturing of equipment for the semiconductor, display, biomedical and other industries. Activities include:o Supporting customer engagements, generating project proposals (incl. cost/schedule estimates)o Working with customers to define requirements, identify scope change and clarify technical matterso Leading system design, integration and test plan definition and execution effortso Manage engineering project deliverables, incl. performance, schedule and NRE/materials budgetso Participate in the development of new company processes, capabilities and strategic directions

Campbell, California

Leading a team of systems and quality engineers working on the development of a new metal 3D printer. Responsibilities include:- Define specifications for, drive selection/design of, and qualify various subsystems, including motion controller, AC and DC uninterruptible power supplies, sieve ultrasonic generator, debris removal capability, etc…- Manage system parameters/schematics (interconnects, IOs, motion control,..)- Define and execute system integration test procedures, develop test fixtures- Coordinate development of factory acceptance tests for beta systems- Support process development activities (troubleshoot system issues, run tests)

San Francisco Bay Area

Led a team of engineers in the development of advanced technologies for the assembly of miniature camera and projection modules. Responsibilities included:- Supporting business development activities, generate SOWs- Driving collaboration with Jabil design (Germany) and manufacturing (China) centers; establishing common product development processes.- Enabling smooth transition into/supporting mass production- Developing strategic plans for the organization, incl. resource forecasts and hiring plans, internal development studies, equipment acquisition plans…- Bringing up new NPI facility in Haifa, Israel (incl. system/process qualification, developing and implementing a hiring plan)

Photon Dynamics - San Jose, Ca

Led a team of R&D scientists in the development and transfer of new technologies for the Array Checker product line (electro-optical tester for LCD/OLED), incl.: - A new CMOS imaging sensor with 60% higher resolution and 70% lower costElectro-optical transducers with improved sensitivity (enabling 50% increase in SNR) and faster response times (up to 2x).- New image processing algorithms, resulting in significant improvements in defect detection in high resolution panels and numerous paid upgrades. - A non-contact OLED array technology based on e-beam induced plasma probes. Successfully proved concept and drafted product business plan.- Responsible for development of next generation flat panel display repair payload based on pulsed DUV/visible lasers- Worked on the development of a new, ALD-based growth method for high performance IGZO films with an external partner- Member of corporate patent committee, contributed to in/organic growth efforts

Photon Dynamics - San Jose, Ca

Developed and documented high-level designs for new Array Checker systems (Gen7-10), including system architecture, interfaces and interconnects, motion control requirements and machine cycle (throughput) modelsManaged Array Checker system development programs. Activities included:- Planning and tracking schedules, budgets and resources- Driving design activities in collaboration with subsystem owners- Leading selection of critical subsystem suppliers. Drive definition of specifications, oversee qualification tests, lead resolution of non-compliance issues.- Setting up top-level BOMs in PLM system; driving procurement- Frequent interactions w. customers throughout Asia, both in the pre-sales phase as well as during program execution- Coordinating system integration and installation activitiesLed a team of system engineers in the development of subsystems, including:- New electronic cabinets, enabling a 30% cost reduction - New a-Si residue detection solutions, enabling >2.5x defect contrast increase- A quasi-telecentric voltage imaging lens assy, enabling > 40% cost reduction- An alignment/defect review camera combo, enabling 50% cost reduction- A scalable, Ethernet-based pattern generator w. increased memory capacity.Led program aimed at development of Gen10 Array Tester using CMOS-based direct capacitive sensing technology. Drove feasibility tests for critical subcomponents (packaging, flight control, probing,..). Successfully proved sensing concept.Led particle reduction efforts at customer site. Performed tests, analyzed results, developed, implemented solutions. Yielded 10 x increase in modulator lifetime.Identified and drove resolution of throughput issues.

San Jose, Ca

- Significantly improved applications support and customer’s perception of RTP dopant activation technology via frequent face-to-face interactions.- Unlocked potential of RTP process by thorough characterization and by proving its applicability for alternate applications, (crystallization, dehydrogenation,…)- Characterized ESD in RTP systems, developed ionization solution reducing ESD below customer specifications, implemented solution in customer systems.- Successfully demonstrated the RTP system’s low oxygen annealing capability.- Organized customer demos; documented process development procedures.- Conducted LTPS market survey and customer penetration projects.

Milpitas, Ca

- Key contributions to the development of an ultra-low temperature process technology for the fabrication of OLED display backplanes on flexible substrates.- Co-developed a comprehensive engineering plan for the company.- Led laser annealing, plasma etching, PVD and lithography process development projects. - Initiated tool and process monitoring procedures and provided training and documentation. - Participated in the development of a high quality ultra-low temperature gate dielectric.- Jump-started operations and led the process technicians in the company’s start-up phase. - Supervised junior and assistant engineers

Livermore, Ca

- Developed LTPS processing techniques (collaboration w. AMAT)- Responsible for the fabrication of an active matrix X-ray imager.- Developed and tested poly-Si diodes fabrication processes for magnetic memory arrays.- Developed and investigated a laser assisted method for the “printing” of semiconductor films.- Responsible for the supervision of students.

Ph.D., Semiconductor Physics

Ph.D. research done at Max-Planck-Institut in Grenoble, France

M. Sc., Applied Physics