Daniel Winkelstein Email & Phone Number

Chapel Hill, Nc, Us

Wilsonville, Or, Us

Architect and chief design engineer for a Zynq-MPU based co-modelling processor board and associated FPGA design and OS. This system provided the processing and interface capability between software-based emulation and the hardware-based FPGA prototyping. I designed the hardware including schematic capture, layout, signal integrity simulation and release to manufacturing. I also built the Petalinux OS required for co-modelling support. Finally I built the FPGA verilog code and C-software necessary for manufacturing BIST.Principle hardware designer for the peripheral interfaces required by the FPGA-based ASIC prototyping system. Peripherals included PCIe Gen3 (RC and EP), NVRAM, Ethernet 1G and 10G, and USB (host and device). I created as set of MicroBlaze embedded processor based designs to allow for automated manufacturing testingTeam member of a design team that is developing the next generation of a ASIC prototyping designs based on the Xilinx VU19P Ultrascale based system.Solved a significant set of issue associated with passing the Class-B EMI emissions as part of homologation testing.

San Diego, Ca, Us

Chief architect and principal hardware designer for three generations of an FPGA-based, ASIC prototyping systems using Xilinx Ultrascale FPGAs for emulation of server-class CPUs. I was the chief architect and lead a design engineer for a team who developed three generations of FPGA-based, ASIC prototyping systems that fully exercise all aspects of a set of datacenter-class CPUs as well as associated peripherals and memory. To the best of my knowledge, I designed the largest FPGA-based ASIC prototyping system in the world with 179 Ultrascale XCVU440 FPGAs housed on 36 PCBs and fully interconnected using a mesh of gigabit-rate LVDS interconnect. I led the design team in the schematic capture, layout, fabrication, and assembly of these systems. I also handled logistics for distribution of these system to other Qualcomm sites world-wide. Upon completion of the hardware design, I was part of a team that partitioned the full ASIC RTL to match the FPGA-based prototyping architecture with the requirement to re-target the ASIC RTL into FPGA bit files. I was personally responsible for operation of the ASIC RTL associated with peripherals, including PCIe, SATA, USB, as well as other low speed peripherals (UART, eMMC, SDcard, I2C, SPI, etc).

Morrisville, Nc, Us

Senior Staff EngineerChief architect and principal hardware designer and hardware/software integration lead for a series of Carrier Ethernet class aggregation and customer premises products.Multi-10Gbps Carrier Ethernet Class Aggregation Product FamilyChief architect and hardware designer: I was personally responsible for the hardware and system design for a 7-card chassis product that supported 8 10GBase-X and 72 1000Base-X Ethernet interfaces. I designed the NPU based distributed dataplane processing complex (using multiple Marvell AX240) that performed high touch Layer-2 and Layer-3 packet processing with a combined bandwidth of 334MPPS. I designed the 20Gbps dataplane interconnect used for card-to-card communication. Additionally, I designed the system wide distributed control plane processing based on the multicore Cavium family of MIPs processors. 1 Gigabit Carrier Ethernet CPE Product Family for Ethernet transport over TDM NetworksChief architect and hardware designer: I was personally responsible for the control plane and dataplane main board design. This product used a Cavium MIPs processor and an Altera FPGA for dataplane and control plane processing. This product had a highly aggressive schedule for a brand new design of conception to customer acceptance of the prototype in only 9 months.

Morrisville, Nc, Us

Chief architect and principal hardware designer for Carrier Ethernet class aggregation and customer premises products.Multi-10Gbps Carrier Ethernet Class Aggregation Product FamilyChief architect and hardware designer: I was personally responsible for the hardware and system design for a 7-card chassis based product that supported 8 10GBase-X and 72 1000Base-X Ethernet interfaces. I designed the NPU based distributed dataplane processing complex (using multiple Marvell AX240) that performed high touch Layer-2 and Layer-3 packet processing with a combined bandwidth of 334MPPS. I designed the 20Gbps dataplane interconnect used for card-to-card communication. Additionally, I designed the system wide distributed control plane processing based on the multicore Cavium family of MIPs processors. 1 Gigabit Carrier Ethernet CPE Product Family for Ethernet transport over TDM NetworksChief architect and hardware designer: I was personally responsible for the control plane and dataplane main board design. This product used a Cavium MIPs processor and an Altera FPGA for dataplane and control plane processing. This product had a highly aggressive schedule: start-to-customer GA in only 9 months for a brand new design.

Meudon, Fr

Principal ScientistSecurity Clearance: Top SecretFounding partner in a startup corporation. Principal hardware and system architect for a set of encryption products for ATM, SONET, Ethernet and IPSEC networks.10 Gigabit Ethernet MACsec Product Line: Chief architect, hardware designer, and FPGA designer for a MACsec, standard based, high performance Ethernet security solution: I designed a high performance 10Gbps Ethernet solution based on XFP transceivers, Marvel 10G PHY devices, Cortina 10G MAC devices and Stratix-II FPGAs. I was personally responsible for the hardware design of the Ethernet encrytion devices including the security and host processor complex. I was personally responsible for ensuring that the Intellectual Property developed, at four geographically remote locations, integrated smoothly in addition to designing the hardware and architecting the system.OC-192 Type-1 SONET Encryption Product Line: Team member and system architect of a 10Gbps Classified SONET encryption product line: I was personally responsible for the hardware design of the 10Gbps SONET interface card and a 2.5Gbps SONET interface card. The design included advanced PLLs for clock management, Agere ASICs, and Altera Stratix-II FPGAs. Additionally, I was responsible for the Verilog HDL design for four large FPGAs.Gigabit IPSEC Gateway Product: Chief hardware architect and designer for a multi-Gigabit IPSEC encryption product based on a dual IXP2400 Network Processor and VxWorks operating system: I designed an embedded Network Processor based dataplane processing system with interfaces to QDR SSRAM, DDR SDRAM and Xilinx Virtex-II FPGAs. ASIC design: Team member of a three-man design team that produced a 250,000 gate ASIC for an OC-3c rate ATM encryption product. ATM encryption product: Architect for an FPGA based ATM encryptor that operated at rates from 1.5Mbps up to 622Mbps full duplex:

Meudon, Fr

Security Clearance: Top SecretFounding partner in a startup corporation. Principal hardware and system architect for a set of encryption products for ATM, SONET, Ethernet and IPSEC networks.10 Gigabit Ethernet MACsec Product Line: Chief architect, hardware designer, and FPGA designer for a MACsec, standard based, high performance Ethernet security solution: I designed a high performance 10Gbps Ethernet solution based on XFP transceivers, Marvel 10G PHY devices, Cortina 10G MAC devices and Stratix-II FPGAs. I was personally responsible for the hardware design of the Ethernet encrytion devices including the security and host processor complex. I was personally responsible for ensuring that the Intellectual Property developed, at four geographically remote locations, integrated smoothly in addition to designing the hardware and architecting the system.OC-192 Type-1 SONET Encryption Product Line: Team member and system architect of a 10Gbps Classified SONET encryption product line: I was personally responsible for the hardware design of the 10Gbps SONET interface card and a 2.5Gbps SONET interface card. The design included advanced PLLs for clock management, Agere ASICs, and Altera Stratix-II FPGAs. Additionally, I was responsible for the Verilog HDL design for four large FPGAs.Gigabit IPSEC Gateway Product: Chief hardware architect and designer for a multi-Gigabit IPSEC encryption product based on a dual IXP2400 Network Processor and VxWorks operating system: I designed an embedded Network Processor based dataplane processing system with interfaces to QDR SSRAM, DDR SDRAM and Xilinx Virtex-II FPGAs. ASIC design: Team member of a three-man design team that produced a 250,000 gate ASIC for an OC-3c rate ATM encryption product. ATM encryption product: Architect for an FPGA based ATM encryptor that operated at rates from 1.5Mbps up to 622Mbps full duplex:

Research Triangle Park, North Carolina, Us

Communications Research EngineerSecurity Clearance: Top SecretPrinciple Investigator and hardware designer for state-of-the-art research projects in communication and network security.ATM traffic analysis and encryption research: Principle investigator of a series of DARPA funded projects to design, build, and test the traffic characteristics and security of OC-12c rate ATM networks: I designed the hardware for the first demonstrable non-classified encryption technology for ATM networks operating at OC-12c rates.ATM networking research: Hardware designer for a DARPA/NFS funded project to prove the feasibility of distributed supercomputing over high speed wide-area networks: I was responsible for the hardware design for an 800Mbps traffic analysis system.

Research Triangle Park, North Carolina, Us

Security Clearance: Top SecretPrinciple Investigator and hardware designer for state-of-the-art research projects in communication and network security.ATM traffic analysis and encryption research: Principle investigator of a series of DARPA funded projects to design, build, and test the traffic characteristics and security of OC-12c rate ATM networks: I designed the hardware for the first demonstrable non-classified encryption technology for ATM networks operating at OC-12c rates.ATM networking research: Hardware designer for a DARPA/NFS funded project to prove the feasibility of distributed supercomputing over high speed wide-area networks: I was responsible for the hardware design for an 800Mbps traffic analysis system.

Ca

PCB design research: I was team leader of a research group that investigated transmission-line effects of printed circuit board design on high-speed digital signals. Central Office switching equipment design: I was part of a group that designed Telco-class central office switching equipment. I was responsible for the design of the power subsystems and cable assemblies.

Masters Of Science, Electrical Engineering

Bachelor Of Science, Computer And Systems Engineering