• Generating new job descriptions, interviewing candidates, and providing junior engineers with critical feedback.• Lead design efforts by coordinating, monitoring, and mentoring junior design engineers on multiple projects.• Break project milestones into component parts and delegate to team members.• Work with cross-functional groups throughout the entire hardware life cycle, including customers + suppliers, as well as hardware, software, integration, test, digital, and RF engineers, to meet the requirements/objectives. • Design, document, and implement RTL for Kintex® and Zynq® Field Programmable Gate Arrays (FPGAs). • Drive tasks to completion with necessary quality to meet milestone objectives • Leverage design habits that lead to area/power efficient while achieving necessary timing constraints. • RTL designs targeting Zynq® System-on-Chip (SoC) and simulation using ModelSim®. • Design system architecture for high speed or multiple CDCs, timing constraining, timing closure. • Utilize knowledge of wireless communications standards: PHY 5G NR and LTE eCPRI 7-2x and 8 splits. • SystemVerilog, Verilog, Python, TCL, Bash and GNU Make

• Work closely with analog teams on functionality, interfaces, and documentation. • Implement and delivery of UVM verified RTL Blocks given system architecture • Participate and develop of DSP algorithms, Micro-architecture specifications with a Formal Design Process • Create simple test benches during design. • Support the Design Verification (DV), Physical Design (PD) and Firmware • Ensure RTL correctness through formal verification using UVM • Respond to issues found by engineers running the Lint, CDC, STA, and Design Compiler (DC) Synthesis. • Experience working with Gate level simulation and debug with VCS and other simulators • Support handoff of RTL blocks to prototyping engineers for integrating the delivered RTL into FPGA platforms. • Maintain Continuous-Integration build environment to produce a high-quality design. • Broad use of scripting in Linux using: Python, TCL, Bash and Make • SystemVerilog RTL front and backend design of Mixed Signal Application Specific Integrated Circuit (ASIC)

• Developed Vector Processor HDL blocks and C to demonstrate Distributed MIMO technology. • Developed SDR functions in C for subcarrier selection, constellation mapping, CFO/SFO. • Designed RISC-V peripherals, SPI, Cross-Correlation, Autocorrelation, and Vector Processor in Verilog. • Performed "Classical" constrained random verification using Verilator and C++. • Efficient implementation of elastic communication channels, pipelined architectures, and hazard avoidance. • Maintain an up-to-date repository by branching, merging, and committing often daily. • Knowledge of digital signal processing: FFT, FIR, IIR and CIC. • Apply knowledge of digital communications and signal processing targeted at Lattice FPGAs. • FPGA Design, Integration, and Test

• Apply knowledge of digital communications and signal processing targeted at FPGA implementations of OFDM. • Architect and implement wireless PHY components in FPGA fabric. • Developed Spread Spectrum, Frequency Estimation, Equalization, Interleaving, Rate Matching pipelined blocks. • Create module and system level test-benches with Functional Verification using QuestaSim® and Riviera Pro®. • Perform constraining, synthesis, timing analysis, closure using Quartus®. • Design in a collaborative environment using Git with merging and conflict resolution. • Implement advanced algorithms written C, Python, and MATLAB® into efficient HDL implementations. • FPGA Design, Integration, and Test

• Supported Research & Development of airborne Electronic Attack and Electronic Protection systems. • Designed and developed FPGA digital hardware using Verilog and VHDL with simulation in ModelSim®. • Interfaced memory and peripheral buses such as I2C, SPI, Multi-gigabit transceivers with FPGAs. • Firmware development with ISE and Vivado® design flows with ModelSim® simulation. • Develop formal test requirements, specifications, and source code/hardware descriptions to release in CM. • Communicate effectively in verbal e.g. day-to-day discussions and team meetings. • FPGA Design, Integration, and Test

• Supported the development and fielding of airborne Signal Intelligence systems. • Designed and developed FPGA digital hardware using Verilog and VHDL with simulation in Modelsim®. • Verified hardware and linked to other groups involved in embedded firmware development. • Developed hardware verification scripts and regression tests using Python and MATLAB®. • Developed specifications, test procedures, memory maps, interconnect diagrams, and release in CM. • Communicate effectively in verbal e.g. day-to-day discussions and team meetings. • FPGA Design, Integration, and Test

Satellite, Wideband & Telemetry Systems Journeyman