Daniel Hull

Daniel Hull Email and Phone Number

PMTS System Design Engineer and Board Design Manager @ AMD
Kirkland, WA, US
Daniel Hull's Location
Greater Seattle Area, United States, United States
Daniel Hull's Contact Details
About Daniel Hull

Expert in server hardware development with strong capabilities as both an individual technical contributor as well as a veteran manager. I have experience building and managing diverse teams responsible for all aspects of server hardware development, including working with CPU and platform architects to drive and advocate end customer use cases, leading teams of engineering specialists in hardware design, power delivery, signal integrity, thermal/mechanical design, and platform architecture. I have experience directly supporting the product development and fleet support for the largest Cloud Service Providers working with AI platforms. I have worked with numerous ODMs including negotiating Statements of Work for reference design development. As an individual contributor I have worked primarily in storage platform architecture, including developing performance models for customer workloads and driving requirements into platform landing zones. I have significant experience in hardware debugging and validation, and have lead numerous system developments from concept through power-on, validation, and final release.

Daniel Hull's Current Company Details
AMD

Amd

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PMTS System Design Engineer and Board Design Manager
Kirkland, WA, US
Daniel Hull Work Experience Details
  • Amd
    Pmts System Design Engineer And Board Design Manager
    Amd
    Kirkland, Wa, Us
  • Zt Systems
    Senior Hardware Engineering Manager
    Zt Systems Mar 2023 - Present
    Secaucus, New Jersey, Us
    Managing a team of hardware engineers responsible to design, build, and deliver high quality, purpose-built cloud-enabling solutions powering CSP datacenters.
  • Intel Corporation
    Manager, Dcai Cloud Hardware Engineering
    Intel Corporation Nov 2020 - Mar 2023
    Santa Clara, California, Us
    • Responsible to build, develop, and manage a team of up to 25 engineers to support all major CSPs (MSFT, Meta, Google, Meta etc) and ODMs for their next generation product architecture and design support. • Team consists of system architects and engineers across platform design, power delivery, signal integrity, thermal/mechanical, and fleet support domains. • Participate and drive architecture and design discussion for next gen cloud products including single socket to multi-socket compute, storage, and other emerging technologies products. • Team responsibilities also included first and second level response to sustaining/fleet issues in response to CSP concerns, driving internal support and communicating status to customers.• Work with executive management to continue to drive efficiencies and priorities for the organization. • Mentor and provide opportunities for the team to grow and develop in their career.
  • Intel Corporation
    Storage Architect
    Intel Corporation Jul 2018 - Nov 2020
    Santa Clara, California, Us
    • Responsible Architect for leading development for Enterprise and Traditional Storage.• Responsible for driving Customer platform requirements to the Inter product. • Lead discussions with Silicon Architects and FW/Software teams to ensure customer requirements can be met. • Define pre-silicon platform performance estimates and requirements • Develop storage pathfinding strategies for 5+ year horizon
  • Intel Corporation
    Manager, Storage Group Hardware Engineering
    Intel Corporation Jan 2009 - Nov 2018
    Santa Clara, California, Us
    • Responsible for the architecture, development, and delivery, at a system and board level, of reference designs for Enterprise, Cloud, and Entry Storage, and Communications reference designs. • Managed a diverse team of up to 17 individual contributors including architecture, design engineers, thermal/mechanical, signal integrity, PCB design, and technicians. • Managed development/validation lab used across organization by 50+ engineers. • Lead and managed multiple internal and On-site Customer Power On. • Drove strategies for future product development and priorities for the organization. • Secured and led engagements with ODM and EMS development partners, internal operations support, and internal platform engineering teams. Directly engaged with ODMs to negotiate Statement of Work and develop contracts for engineering support on storage reference designs.• Forecast and managed BTI and capital budgets, responsible for managing all Chandler DCG

Daniel Hull Education Details

  • Milwaukee School Of Engineering
    Milwaukee School Of Engineering
    Electrical Engineering

Frequently Asked Questions about Daniel Hull

What company does Daniel Hull work for?

Daniel Hull works for Amd

What is Daniel Hull's role at the current company?

Daniel Hull's current role is PMTS System Design Engineer and Board Design Manager.

What is Daniel Hull's email address?

Daniel Hull's email address is da****@****tel.com

What schools did Daniel Hull attend?

Daniel Hull attended Milwaukee School Of Engineering.

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